US 2003/0159013 A1 · Memory controller system and methods thereof

Abstract

A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible. If the bypass is possible, the second memory request is cancelled.

Claims39

Dependent claims

A method comprising the steps of:

providing, to a client, a signal indicating a state of a memory controller pipeline;
receiving a memory access request from the client, the memory access request to obtain data from a page of memory by bypassing a portion of the memory controller pipeline;
determining, after receiving the memory access request from the client, if the page of memory is open;
and
delivering the memory access request to a later portion of the memory controller pipeline, wherein an earlier portion of the memory controller pipeline, used to process the memory access request before the later portion, is bypassed.

2 more elements

A system comprising:

a client interface to:
receive a memory access request to access data from memory, wherein the memory access request is provided by a memory client;
receive a signal indicating an activity of a first component of a memory controller;
provide the memory access request to the first component when the signal indicates the first memory component is busy;
providing the memory access request to a bypass module when the signal indicates the first component is idle;
said memory controller including:
said first component to:
organize the memory access request with pending memory requests;
provide the memory request to a second component;
a second component to:
arbitrate the memory access request with pending memory requests;
provide the memory access request to a memory request sequencer;
a memory request sequencer to queue memory requests to memory;
a bypass module to:
identify activity associated with the first component, the second component, and the memory request sequencer;
provide the signal indicating the activity of the first component to the client interface;
receive the memory access request from the client interface;
determine whether the memory access request is valid for processing in the memory request sequencer;
providing the memory access request to the second component when the memory access request is valid;
providing the memory access request to the second component when the memory access request is valid;
and
a memory to provide data associated with the memory access request.

19 more elements

Dependencies are inferred from the claim text.

Memory controller system and methods thereof

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Memory controller system and methods thereof

Life of this patent

Abstract

Claims39