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US 2003/0159008 A1Published application
Method and apparatus to control memory accesses
AssigneeIntel Corporation
InventorsEric A. Sprangle, Onur Mutlu
Life of this patent
Estimating the term…
Abstract
A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher; determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core; and switching memory accesses from a first mode to a second mode if a percentage of the memory access generated by the hardware prefetcher are used by the out-of-order core.
Claims30
An apparatus for accessing memory comprising:
- a page open predictor to predict open memory pages;
- a front side bus scheduler to switch memory access modes from a first mode to a second mode, said front side bus scheduler coupled to the page open predictor;
- and
- a front side bus access queue, coupled to the front side bus scheduler, to contain memory accesses.
1 more element
A method comprising:
- monitoring memory accesses generated by a hardware prefetcher;
- determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core;
- and
- switching memory accesses from a first mode to a second mode if a percentage of the memory accesses generated by the hardware prefetcher are used by the out-of-order core.
1 more element
A computer system comprising:
- a bus;
- a processor coupled to the bus;
- a front side bus controller coupled to the bus, said front side bus controller comprising a page open predictor, and a front side bus scheduler, said front side bus scheduler to switch memory access modes from a first mode to a second mode, said front side bus scheduler coupled to the page open predictor;
- and
- a front side bus access queue, coupled to the front side bus scheduler, to contain memory accesses.
2 more elements
Dependencies are inferred from the claim text.