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AssigneeIP-First, LLC
InventorsDarius D. Gaskins, James Hardage
Estimating the term…
An associative cache memory having an integrated tag and LRU array storing pseudo-LRU information on a per way basis, obviating the need for a separate LRU array storing pseudo-LRU information on a per row basis. Each way of the integrated array stores decoded bits of pseudo-LRU information along with a tag. An encoder reads the decoded bits from all the ways of the selected row and encodes the decoded bits into standard pseudo-LRU form. The control logic selects a replacement way based on the encoded pseudo-LRU bits. The control logic then generates new decoded pseudo-LRU bits and updates only the replacement way of the selected row with the new decoded pseudo-LRU bits. Thus, the control logic individually updates only the decoded bits of the replacement way concurrent with the tag of the replacement way, without requiring update of the decoded bits in the non-replacement ways of the row.
An N-way associative cache memory, comprising:
An N-way associative cache memory, comprising:
A 4-way associative cache, comprising:
An associative cache memory having an integrated tag and cache line replacement information array, comprising:
An N-way associative cache memory, comprising:
A method for updating an associative cache having M rows and N ways, comprising the steps of:
Dependencies are inferred from the claim text.