US 2003/0158981 A1Published application

Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing

AssigneeMicron Technology, Inc.

InventorPaul A. LaBerge

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Abstract

A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.

Claims33

Dependent claims

A method of transferring read data from a memory device, the memory device including a data bus and including at least one data masking pin adapted to receive a data masking signal during write operations of the memory, the method comprising:

placing a current read data word on the data bus, the read data word including a plurality of data signals and each data signal having a logic state;
developing a next read data word, the next read data word including a plurality of data signals and each data signal having a logic state;
comparing the logic state of each data signal in the current read data word to the logic state of the corresponding data signal in the next read data word;
determining the number of data signals in the next read data word that are changing from a first logic state in the current read data word to the complementary logic state in the next read data word;
when the determined number of data signals changing from the first logic state to the complementary logic state is greater than N,
developing an inverted next read data word, each data signal in the inverted next read data word having a logic state that is the complementary logic state of the corresponding data signal in the next read data word, and
activating a data bus inversion signal;
placing the inverted next read data word on the data bus;
and
applying the activated data bus inversion signal on one of the data masking pins.

7 more elements

A method of transferring read data from a memory device, the memory device including a data bus and including a data masking pin adapted to receive a masking signal during write operations of the memory device, the method comprising:

placing a sequence of read data words on the data bus;
and
applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted.

A memory device, comprising:

an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
a data masking terminal adapted to receive a data masking signal during write operations of the memory device;
and
a read/write circuit coupled to the data bus, memory-cell array, and the data masking terminal, the read/write circuit operable during read operations to compare the number of bits changing from a first logic state in a current read data word on the data bus to the complementary logic state in a next read data word received from the memory-cell array, and operable in a first mode when the number of bits changing state is greater than a threshold value to apply an inverted next read data word on the data bus and apply an active a data bus inversion signal on the data masking terminal, and operable in a second mode when the number of bits changing state is less than or equal to the threshold value to apply the next read data word on the data bus and apply an inactive data bus inversion signal on the data masking terminal.

6 more elements

A computer system, comprising:

a data input device;
a data output device;
a processor coupled to the data input and output devices;
and
a memory device coupled to the processor, the memory device comprising,
an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
a data masking terminal adapted to receive a data masking signal during write operations of the memory device;
and
a read/write circuit coupled to the data bus, memory-cell array, and the data masking terminal, the read/write circuit operable during read operations to compare the number of bits changing from a first logic state in a current read data word on the data bus to the complementary logic state in a next read data word received from the memory-cell array, and operable in a first mode when the number of bits changing state is greater than a threshold value to apply an inverted next read data word on the data bus and apply an active a data bus inversion signal on the data masking terminal, and operable in a second mode when the number of bits changing state is less than or equal to the threshold value to apply the next read data word on the data bus and apply an inactive data bus inversion signal on the data masking terminal.

11 more elements

Dependencies are inferred from the claim text.