Booth encoder and partial products circuit

A Booth encoder circuit comprising:

• a plurality of transistors to receive a plurality of multiplier bits and complements of said plurality of multiplier bits;
• and
• a plurality of logic circuits coupled to ones of said plurality of transistors to output Booth encoded signals.

A multiplier circuit comprising logic to receive a plurality of multiplier bits and complements of said multiplier bits, said logic to output Booth encoded signals based on said multiplier bits and complements of said multiplier bits, said logic configured to have a maximum of three gate delays from an input of said multiplier circuit to an output of said multiplier circuit.

A circuit comprising logic to receive a plurality of multiplier bits and complements of said multiplier bits, said logic including a plurality of transistors, a plurality of NAND gates and a plurality of inverters configured to output delay-matched Booth encoded signals based on said multiplier bits and said complements.

A partial products generator circuit comprising:

• a first multiplexing device having a plurality of first transistors to receive Booth encoded signals and to provide a first partial products output;
• and
• a second multiplexing device having a plurality of second transistors to receive said Booth encoded signals and multiplexed data from said first multiplexing device and to provide a second partial products output.

A partial products generator circuit comprising a multiplexing device to receive Booth encoded signals and to provide a first partial product output for a first bit of a multiplicand based at least on multiplexed data from a previous multiplexing device.