US 2003/0158689 A1 · Method for extracting parasitic capacitances of field-effect transistors

Abstract

The purpose of the present invention is to provide a method to extract the extrinsic capacitances of FETs by a physically-meaningful capacitive transmission line model and a linear regression technique. The method of the present invention includes method includes steps of (a) applying a gate-to-source voltage to pinch-off said FETs and setting a drain-to-source voltage to be zero for forming pinched-off cold FETs, (b) measuring S-parameters of said pinched-off cold FETs, (c) representing an intrinsic depletion region of said pinched-off cold FETs by a distributed capacitive transmission line model having a distributed series capacitance Cs and a distributed parallel capacitance Cp; and (d) executing an analytical procedure according to said measured S-parameters for obtaining Y-parameters.

Claims18

Dependent claims

A method for extracting extrinsic capacitances for FETs, wherein each said FET has a gate, a drain, and a source, comprising steps of:

(a) applying a gate-to-source voltage to pinch-off said FETs and setting a drain-to-source voltage to be zero for forming pinched-off cold FETs;
(b) measuring S-parameters of said pinched-off cold FETs;
(c) representing an intrinsic depletion region of said pinched-off cold FETs by a distributed capacitive transmission line model having a distributed series capacitance Cs and a distributed parallel capacitance Cp;
and
(d) executing an analytical procedure according to said measured S-parameters for obtaining Y-parameters.

2 more elements

A method for FETs to build up a small-signal equivalent circuit, wherein each said FETs has a gate, a drain, and a source, comprising steps of:

(a) applying a gate-to-source voltage to pinch-off said FETs and setting a drain-to-source voltage to be zero for obtaining pinched-off cold FETs;
(b) measuring S-parameters of said piched-off cold FETs FETs;
(c) representing an intrinsic depletion region of said pinched-off cold FETs by a distributed capacitive transmission line model having a distributed series capacitance Cs and a distributed parallel capacitance Cp;
(d) executing an analytical procedure according to said measured S-parameters for obtaining a relation equation of an extrinsic gate capacitance Cpg and an extrinsic drain capacitance Cpd;
and
(e) building up said small-signal equivalent circuit of said FETs by said relation equation of said extrinsic gate capacitance Cpg and said extrinsic drain capacitance Cpd.

3 more elements

Dependencies are inferred from the claim text.

Method for extracting parasitic capacitances of field-effect transistors

Life of this patent

Method for extracting parasitic capacitances of field-effect transistors

Life of this patent

Abstract

Claims18