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US 2003/0157805 A1Published application
Thick traces from multiple damascene layers
AssigneeLSI Logic Corporation
InventorsRichard T. Schultz, Peter J. Wright
Life of this patent
Estimating the term…
Abstract
Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.
Claims16
A method for forming a thick signal trace in an integrated circuit comprising:
- forming a first layer of dielectric;
- etching said first layer of dielectric to form a first trench using a first pattern;
- filling said first trench with a conductive material to form a first electrical trace having a top surface;
- forming a second layer of dielectric;
- etching said second layer of dielectric to form a second trench using a second pattern, said second trench substantially fully exposing said top surface of said first electrical trace;
- and
- filling said second trench with said conductive material forming a second electrical trace having a bottom surface substantially conterminous with said top surface of said first trace.
4 more elements
A trace in an integrated circuit formed by a process that comprises:
- forming a first layer of dielectric;
- etching said first layer of dielectric to form a first trench;
- filling said first trench with an encapsulating material;
- filling said first trench with a conductive material to form an electrical trace having a top surface;
- forming a second layer of dielectric;
- etching said second layer of dielectric to form a second trench, said second trench substantially exposing said top surface of said electrical trace;
- filling said second trench with said encapsulating material;
- filling said second trench with said conductive material forming a second electrical trace having a bottom surface substantially coterminous with said top surface of said electrical trace;
- and
- covering said conductive material with said encapsulating material.
7 more elements
A power trace in an integrated circuit comprising:
- a first conductor being formed in a dielectric layer and having a top surface, said first conductor having an encapsulant formed on the bottom and sides of said first conductor;
- a second conductor, said second conductor having a bottom surface formed conterminous with said top surface of said first conductor, said second conductor having an encapsulant formed on the bottom and sides of said second conductor;
- and
- said dielectric material having a dielectric constant, said dielectric constant being selected to effect the capacitive coupling of said power trace.
1 more element
A capacitor in an integrated circuit comprising:
- a first signal trace and a second signal trace fabricated in at least one signal layer, said signal layer having a first dielectric material;
- at least two electrodes, each electrode being formed in a plurality of successive electrode layers comprising a second dielectric material;
- said electrodes being comprised of conductors formed in said successive layers, each of said conductors having a top surface and a bottom surface wherein said bottom surface is conterminous with said top surface for each of said successive layers;
- and
- wherein said first signal trace and said second signal trace are connected to alternating electrodes.
2 more elements
An inductor in an integrated circuit comprising:
- successive layers comprising a top layer, at least one intermediate layer, and a bottom layer;
- said intermediate layer comprising a plurality of concentric loops, each loop being disunited at two points substantially opposite each other;
- said loops being comprised of conductors formed in said successive layers, each of said conductors having a top surface and a bottom surface wherein said bottom surface is conterminous with said top surface for each of said successive layers;
- and
- said top layer further comprising at least one trace connecting at least two of said concentric loops.
2 more elements
An inductor in an integrated circuit comprising:
- a coiled trace formed in a plurality of successive layers, said coiled trace being comprised of conductors in successive layers, each of said conductors having a top surface and a bottom surface wherein said bottom surface is conterminous with said top surface for each of said successive layers, said layers further comprising a first non-conductive material, said coiled trace having a first end and a second end;
- a first signal trace and a second signal trace in a signal layer, said signal layer comprising a second non-conductive material;
- said first signal trace being in electrical communication with said first end of said coiled trace;
- and
- said second signal trace being in electrical communication with said second end of said coiled trace.
2 more elements
Dependencies are inferred from the claim text.