Etch stop layer for silicon (si) via etch in three-dimensional (3-d) wafer-to-wafer vertical stack
AssigneeIntel Corporation
InventorsSarah E. Kim, R. Scott List, Tom Letson
Life of this patent
Estimating the term…
Abstract
A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
Claims18
A method of forming a vertically stacked wafer structure, comprising:
- forming a contact plug on selected metallic lines of a top wafer;
- forming an etch stop layer on the contact plug;
- selectively etching through a silicon (Si) of the top wafer until stopped by the etch stop layer to form a Si via;
- depositing an oxide layer to insulate a sidewall of the Si via;
- forming a barrier layer on the Si via;
- and
- filling the Si via with a conduction metal to provide electrical connection between active IC devices located on vertically stacked wafers that are included in the vertically stacked wafer structure and an external interconnect.
A method of forming vertically stacked wafers, comprising:
- forming a plurality of metallic lines on opposing surfaces of top and bottom wafers;
- forming a contact plug on a selected metallic line of the top wafer;
- forming an etch stop layer on the contact plug;
- bonding the adjacent wafers, via respective metallic lines, to form vertically stacked wafers;
- and
- forming an interwafer via on the top wafer by selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer, depositing an oxide layer to insulate a sidewall of the interwafer via, depositing a barrier layer on the oxide layer and on the bottom of the interwafer via, and filling the interwafer via with a conduction metal to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
A three-dimensional (3-D) vertically stacked wafer structure, comprising:
- a first wafer including an active layer to support one or more integrated circuit (IC) devices;
- a second wafer including an active layer to support one or more integrated circuit (IC) devices;
- metallic lines deposited on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and electrical connections between active IC devices on the first and second wafers in the stack;
- and
- one or more interwafer vias formed within the first wafer, to provide electrical connections between active IC devices on the first and second wafers in the stack and an external interconnect,
- wherein each of the interwafer vias comprises:
- a contact plug in contact with selected metallic lines of the top wafer;
- an etch stop layer deposited on the contact plug;
- an oxide layer deposited to insulate a sidewall of the via;
- and
- a barrier layer and a conduction metal deposited in the via to provide electrical connection between active IC devices on the first and second wafers in the stack and an external interconnect.
Dependencies are inferred from the claim text.