Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
AssigneeIntel Corporation
InventorsScot A. Kellar, Sarah E. Kim, R. Scott List
Life of this patent
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Abstract
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.
Claims20
A wafer bonding method, comprising:
- forming an interlevel dielectric (ILD) on opposing surfaces of adjacent wafers each wafer including one or more active integrated circuit (IC) devices;
- a selectively depositing metallic lines, via the ILD, on opposing surfaces of the adjacent wafers;
- selectively recessing the ILD surrounding the metallic lines deposited via the ILD to facilitate direct metal bonding between the adjacent wafers;
- selectively aligning the adjacent wafers to form a stack;
- and
- bonding the metallic lines on the surface of one wafer with the metallic lines on the surface of the other wafer to establish electrical connections between active IC devices on the adjacent wafers.
A three-dimensional (3-D) integrated chip system, comprising:
- a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) for wafer-to-wafer bonding and electrical interconnection, and an ILD recess surrounding the metallic lines deposited via the ILD;
- and
- a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) for wafer-to-wafer bonding and electrical interconnection, and an ILD recess surrounding the metallic lines deposited via the ILD, wherein the metallic lines on the surface of the second wafer are bonded with the metallic lines on the surface of the first wafer to establish electrical connections between active IC devices on the adjacent wafers.
A three-dimensional (3-D) integrated chip system, comprising:
- a first wafer including one or more integrated circuit (IC) devices;
- a second wafer including one or more integrated circuit (IC) devices;
- and
- metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.
Dependencies are inferred from the claim text.