US 2003/0157770 A1 · Method of making the selection gate in a split-gate flash eeprom cell and its structure

Abstract

A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.

Claims26

Dependent claims

A method for manufacturing the selection gate of a split-gate flash EEPROM cell applied to a semiconductor substrate formed with a suspending gate structure with at least a gate oxide/polysilicon/first oxide and a source, the method comprising the steps of:

forming a trench in the semiconductor substrate on one side of the suspending gate structure, the trench being located opposite to the drain;
forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench;
forming a polysilicon spacer on the sidewall of the inter polysilicon dielectric layer as the selection gate;
and
forming a drain on the semiconductor substrate in the trench, the drain being adjacent to the selection gate.

2 more elements

A method for manufacturing a split-gate flash EEPROM cell comprising the steps of:

forming a gate oxide layer on a semiconductor substrate;
forming a polysilicon layer on the gate oxide layer;
forming a silicon nitride layer on the polysilicon layer;
forming a trench in the silicon nitride layer and exposing part of the upper surface of the polysilicon layer to define a suspending gate region;
forming a first oxide layer in the trench;
forming a common source plug between two of the adjacent suspending gate regions;
performing etching to remove the silicon nitride layer and the polysilicon layer and the gate oxide layer not covered by the first oxide layer, forming a suspending gate structure;
forming a substrate trench in the semiconductor substrate on one side of the suspending gate structure, the substrate trench being located opposite to the common source plug;
forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the substrate trench;
forming a polysilicon spacer on the inter polysilicon dielectric sidewall as the selection gate;
and
forming a drain on the semiconductor substrate in the trench, the drain being adjacent to the selection gate.

9 more elements

Dependencies are inferred from the claim text.

Method of making the selection gate in a split-gate flash eeprom cell and its structure

Life of this patent

Method of making the selection gate in a split-gate flash eeprom cell and its structure

Life of this patent

Abstract

Claims26