US 2003/0157757 A1 · Method of manufacturing a semiconductor integrated circuit device

Abstract

Oxidation on the surface of a film of refractory metal constituting a gate electrode (word line WL) is suppressed by forming an insulation film constituting a cap insulation film of the gate electrode (word line WL) at a temperature of 500° C. or lower. Further, oxidation on the surface of the refractory metal film exposed to the side wall of the gate electrode (word line WL) is suppressed by forming an insulation film constituting the side wall spacer of the gate electrode (word line WL) at a temperature of 500° C. or lower.

Claims26

Dependent claims

A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising:

(a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,
(b) a step of forming a gate electrode by etching the first insulation film and the gate electrode material using a photoresist as a mask,
(c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region,
(d) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the gate electrode at a temperature of 500° C. or lower and then etching the second insulation film, to form a side wall spacer to the side wall of the gate electrode and the first insulation film, and
(e) a step of depositing a third insulation film having an etching rate different from those of the first and the second insulation films over the gate electrode and then etching the third insulation film using a photoresist as a mask, to form a contact hole for the connection of wiring to one of the source region and the drain region.

2 more elements

A method of manufacturing a semiconductor integrated circuit device having MISFET, comprising:

(a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,
(b) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the first insulation film at a temperature of 500° C. or higher and then etching the second insulation film, the first insulation film and the gate electrode material using a photoresist as a mask, to form a gate electrode,
(c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region,
(d) a step of depositing a third insulation film having an etching rate approximately identical with that of the first and the second insulation films over the gate electrode at a temperature of 500° C. or lower, depositing a fourth insulation film having an etching rate approximately identical with that of the third insulation film at a temperature of 500° C. or higher over the third insulation film and then etching the fourth and the third insulation films, to form a side wall spacer on the side wall of the gate electrode and the first and the second insulation films, and
(e) a step of depositing a fifth insulation film having an etching rate different from those of the first to fourth insulation films over the gate electrode and then etching the fifth insulation film by using a photoresist as a mask, to form a contact hole for connection of wiring to one of the source region and the drain region.

2 more elements

A method of manufacturing a semiconductor integrate circuit device having a DRAM provided with a memory cell of a stacked capacitor structure in which bit lines are disposed over a memory selection MISFET and information storage capacitors are disposed over the bit lines, comprising:

(a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,
(b) a step of etching the first insulation film and the gate electrode material using a photoresist as a mask, to form a gate electrode for a memory cell selection MISFET,
(c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region of a memory cell selection MISFET,
(d) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the gate electrode at a temperature of 500° C. or lower and then etching the second insulation film, to form a side wall spacer to the side wall of the gate electrode and the first insulation film,
(e) a step of depositing a third insulation film having an etching rate different from those of the first and the second insulation films over the gate electrode and then etching the third insulation film by using a photoresist as a mask, to form a first contact hole for the connection of a bit line to one of the source region and the drain region, and a second contact hole for connection of a lower electrode of the information storage capacitor to the other of the source region and the drain region,
(f) a step of burying plugs to the inside of the first and the second contact holes, depositing a bit line material containing at least one layer of a metal film over the third insulation film and then depositing a fourth insulation film over the bit line material at a temperature of 500° C. or lower,
(g) a step of etching the fourth insulation film and the bit line material by using a photoresist as a mask to form a bit line,
(h) a step of depositing a fifth insulation film having an etching rate approximately identical with that of the fourth insulation film over the bit line at a temperature of 500° C. or lower and then etching the fifth insulation film, to form a side wall spacer to the side wall of the bit line and the fourth insulation film, and
(i) a step of depositing a sixth insulation film having an etching rate different from those of the fourth and fifth insulation films over the bit line and then etching the sixth insulation film by using a photoresist as a mask, to form a third contact hole over the second contact hole for connecting the lower electrode of the information storage capacitor and the other of the source region and the drain region.

6 more elements

A method of manufacturing a semiconductor integrated circuit device having a MISFET with source, drain and gate, comprising:

(a) a step of depositing a first conductive film of a refractory metal over a main surface of a semiconductor substrate, a first silicon nitride film on the first conductive film and a second silicon nitride film on the first silicon nitride film,
(b) a step of fabricating the first conductive film and the first and the second silicon nitride films into a predetermined pattern, to form a gate electrode of the MISFET,
(c) a step of introducing impurities into the semiconductor substrate in an self-alignment manner to the gate electrode for forming semiconductor regions that function as the source and the drain,
(d) a step of depositing a third silicon nitride film on the gate electrode and a fourth silicon nitride film on the third silicon nitride film,
(e) a step of applying anisotropic etching to the third and the fourth silicon nitride films, to form a side wall spacer on the side wall of the gate electrode,
(f) a step of depositing an oxide film over the gate electrode and the side wall spacer, and
(g) a step of applying etching to the oxide film for forming an opening to the oxide film for exposing a portion of the semiconductor region,
wherein the first silicon nitride film is formed at a temperature lower than that for the second silicon nitride film, and the third silicon nitride film is formed at a temperature lower than that for the fourth silicon nitride film.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/365,423Filed 13 Feb 2003

Priority

JP 8-13604430 May 1996

Published

21 Aug 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10B 12/488
Data lines or contacts therefor: word lines
H10P 14/412
Of conductive or resistive materials: deposition of metallic or metal-silicide materials
H10W 10/0126
Comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics: introducing electrical…

Family

Application08/865,706Continuation · filed 30 May 1997

Application09/741,810Continuation · filed 22 Dec 2000

Application10/365,423Continuation · filed 13 Feb 2003

US 2001/0001717 A1Published application

US 6,852,579 B2Related patent

US 2003/0157757 A1This patent

From the US filing history. Foreign family members aren’t listed.

Abstract

Claims26

Dependent claims

A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising:

(a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,
(b) a step of forming a gate electrode by etching the first insulation film and the gate electrode material using a photoresist as a mask,
(c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region,
(d) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the gate electrode at a temperature of 500° C. or lower and then etching the second insulation film, to form a side wall spacer to the side wall of the gate electrode and the first insulation film, and
(e) a step of depositing a third insulation film having an etching rate different from those of the first and the second insulation films over the gate electrode and then etching the third insulation film using a photoresist as a mask, to form a contact hole for the connection of wiring to one of the source region and the drain region.

2 more elements

A method of manufacturing a semiconductor integrated circuit device having MISFET, comprising:

(a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,
(b) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the first insulation film at a temperature of 500° C. or higher and then etching the second insulation film, the first insulation film and the gate electrode material using a photoresist as a mask, to form a gate electrode,
(c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region,
(d) a step of depositing a third insulation film having an etching rate approximately identical with that of the first and the second insulation films over the gate electrode at a temperature of 500° C. or lower, depositing a fourth insulation film having an etching rate approximately identical with that of the third insulation film at a temperature of 500° C. or higher over the third insulation film and then etching the fourth and the third insulation films, to form a side wall spacer on the side wall of the gate electrode and the first and the second insulation films, and
(e) a step of depositing a fifth insulation film having an etching rate different from those of the first to fourth insulation films over the gate electrode and then etching the fifth insulation film by using a photoresist as a mask, to form a contact hole for connection of wiring to one of the source region and the drain region.

2 more elements

(a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,
(b) a step of etching the first insulation film and the gate electrode material using a photoresist as a mask, to form a gate electrode for a memory cell selection MISFET,
(c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region of a memory cell selection MISFET,
(d) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the gate electrode at a temperature of 500° C. or lower and then etching the second insulation film, to form a side wall spacer to the side wall of the gate electrode and the first insulation film,
(e) a step of depositing a third insulation film having an etching rate different from those of the first and the second insulation films over the gate electrode and then etching the third insulation film by using a photoresist as a mask, to form a first contact hole for the connection of a bit line to one of the source region and the drain region, and a second contact hole for connection of a lower electrode of the information storage capacitor to the other of the source region and the drain region,
(f) a step of burying plugs to the inside of the first and the second contact holes, depositing a bit line material containing at least one layer of a metal film over the third insulation film and then depositing a fourth insulation film over the bit line material at a temperature of 500° C. or lower,
(g) a step of etching the fourth insulation film and the bit line material by using a photoresist as a mask to form a bit line,
(h) a step of depositing a fifth insulation film having an etching rate approximately identical with that of the fourth insulation film over the bit line at a temperature of 500° C. or lower and then etching the fifth insulation film, to form a side wall spacer to the side wall of the bit line and the fourth insulation film, and
(i) a step of depositing a sixth insulation film having an etching rate different from those of the fourth and fifth insulation films over the bit line and then etching the sixth insulation film by using a photoresist as a mask, to form a third contact hole over the second contact hole for connecting the lower electrode of the information storage capacitor and the other of the source region and the drain region.

6 more elements

A method of manufacturing a semiconductor integrated circuit device having a MISFET with source, drain and gate, comprising:

(a) a step of depositing a first conductive film of a refractory metal over a main surface of a semiconductor substrate, a first silicon nitride film on the first conductive film and a second silicon nitride film on the first silicon nitride film,
(b) a step of fabricating the first conductive film and the first and the second silicon nitride films into a predetermined pattern, to form a gate electrode of the MISFET,
(c) a step of introducing impurities into the semiconductor substrate in an self-alignment manner to the gate electrode for forming semiconductor regions that function as the source and the drain,
(d) a step of depositing a third silicon nitride film on the gate electrode and a fourth silicon nitride film on the third silicon nitride film,
(e) a step of applying anisotropic etching to the third and the fourth silicon nitride films, to form a side wall spacer on the side wall of the gate electrode,
(f) a step of depositing an oxide film over the gate electrode and the side wall spacer, and
(g) a step of applying etching to the oxide film for forming an opening to the oxide film for exposing a portion of the semiconductor region,
wherein the first silicon nitride film is formed at a temperature lower than that for the second silicon nitride film, and the third silicon nitride film is formed at a temperature lower than that for the fourth silicon nitride film.

5 more elements

Dependencies are inferred from the claim text.

Method of manufacturing a semiconductor integrated circuit device

Life of this patent

Abstract

Claims26

Method of manufacturing a semiconductor integrated circuit device

Life of this patent

Abstract

Claims26