Mos integrated circuit with reduced on resistance

A method of making an integrated circuit having a high voltage lateral MOS in an island region of a first conductivity type, the method comprising:

• introducing a high density impurity of a second conductivity type in the island region to form a drain contact;
• introducing a high density impurity of the second conductivity type in the island region to form a source, wherein the source is formed a predetennined lateral distance from the drain;
• forming a gate dielectric on a portion of the island surface between the source and the drain contact;
• fonning a gate on a portion of the gate dielectric, wherein the gate dielectric is positioned between the gate and the island surface;
• introducing the second conductivity type impurity in the island region to form a first drain extension, wherein the first drain extension extends laterally from the drain contact to underneath a portion of the gate;
• and
• introducing the second conductivity type impurity in the island region to form a second drain extension, wherein the second drain extension extends laterally from a position proximate the source to overlap the first drain extension underneath the gate.