Scrambler with scramble process bypass capability and descrambler with descramble process bypass capability

A scrambler carrying out a process in parallel, comprising:

• m registers;
• and
• m exclusive OR gates;
• where m is an integer of at least 2;
• said m registers holding scrambled data,
• said m exclusive OR gates respectively having each bit of transmission data input, and an output of said register selectively input according to a generating polynomial;
• and
• said scrambler further comprising a circuit driving outputs of said m registers to a low level in a transmission data bypass mode.

A descrambler comprising:

• m registers connected in series;
• m exclusive OR gates;
• and
• m−1 switches turned on/off according to a generating polynomial;
• where m is an integer of at least 2 and i is an arbitrary integer of at least 1 and not more than m−1,
• scrambled data being input to a first register and a first exclusive OR gate,
• an output of an i-th register being input to an (i+1)th exclusive OR gate via an i-th switch,
• an output of the (i+1)th exclusive OR gate being input to an i-th exclusive OR gate,
• an output of an m-th register being input to an m-th exclusive OR gate,
• the (i+1)th exclusive OR gate carrying out an exclusive OR operation when the i-th switch is on, and the (i+1)th exclusive OR gate directly outputting a value of a terminal to which the switch is not connected when the i-th switch is off;
• and
• said descrambler further comprising a circuit outputting a low level to one terminal of said first exclusive OR gate to which scrambled data is not input is a scrambled data bypass mode.

A descrambler carrying out a process in parallel, comprising:

• m registers;
• and
• m exclusive OR gates;
• where m is an integer of at least 2,
• said m registers holding previous scrambled data,
• said m exclusive OR gates respectively having each bit of scrambled data input, and an output of said register selectively input according to a generating polynomial;
• and
• said descrambler further comprising a circuit driving outputs of said m registers to a low level in a scrambled data bypass mode.