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US 2003/0156674 A1Published application
Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
AssigneeEmulex Corporation
InventorsJim Butler, Raul Oteyza
Life of this patent
Estimating the term…
Abstract
A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.
Claims7
A method comprising:
- correcting for skew between a first clock signal and a second clock signal in response to selecting a first phase-locked loop circuit feedback path;
- and
- introducing a desired degree of skew between the first clock signal and the second clock signal in response to selecting a second phase-locked loop circuit feedback path.
Apparatus comprising:
- an input node operative to receive a first clock signal;
- an output node operative to receive a second clock signal;
- a phase-locked loop circuit including a first feedback path and a second feedback path, each of said feedback paths operative to introduce a different degree of skew between the first clock signal and the second clock signal;
- and
- a feedback path selector operative to select one of said feedback paths.
2 more elements
Apparatus comprising:
- an input node operative to receive an input signal;
- an output node operative to receive an output signal;
- a clock signal path between the input node and the output node, said clock signal path including a clock tree;
- a phase-locked loop circuit including
- a first feedback path including the clock tree,
- a second feedback path including a string of buffers, and
- a mode selector operative to select the first feedback path in a first operating mode and to select the second feedback path in a second operating mode.
4 more elements
Dependencies are inferred from the claim text.