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AssigneeMicronas GmbH
InventorsAndreas Schoene, Hartmut Beintken
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In order to generate a clock signal (fT1) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (fT1) is generated from a high-frequency clock pulse (f0) and the reference signal (FBAS) is digitized therewith. In addition, a second clock pulse (fT1) is generated from the high-frequency clock pulse (f0) and the phase deviation between the first clock pulse (fT2) and the second clock pulse (fT1) is determined. The digitized sampling values of the reference signal (FBAS) at the first clock frequency (fT1) are converted, according to the phase deviation determined, into corresponding digitized sampling values having the second clock frequency (fT1) and are used as a target specification for generating the second clock pulse (fT1) thus coupled to the reference signal.
Method for generating a clock signal coupled to a reference signal, comprising the steps:
Method according to one of the foregoing claims, characterized in that in step f) an interpolation is performed on the sampling values, provided in step c), of the reference signal (FBAS) at the frequency of the first clock signal (fT2), and on the basis of the phase deviation determined in step e), wherein the interpolated digitized sampling values of the reference signal (FBAS) thus obtained are used in step d) as the target specification to generate the second clock signal (fT1).
Method according to one of the foregoing claims, characterized in that a linear interpolation is performed in step f).
Method according to one of the foregoing claims, characterized in that the second clock signal (fT1) is generated in step d) with the aid of a digital phase-locked loop (7, 8).
Method according to one of the foregoing claims, characterized in that a high-frequency quartz-coupled clock signal is used as the operating clock signal (f0).
Method according to one of the foregoing claims, characterized in that the sampling values of the reference signal (FBAS) supplied in step c) are temporarily stored at the frequency of the second clock signal (fT1) before their use in the conversion effected in step f), and are subsequently used only for the conversion.
Method according to one of the foregoing claims, characterized in that in step b) the first clock signal (fT2) is generated by evaluating the count of a counter (9) operated with the operating clock signal (f0).
Device for generating a clock signal coupled to a reference signal, comprising:
Device according to one of the foregoing claims, in which the conversion device (6) outputs digitized sampling values.
Device according to one of the foregoing claims, characterized in that the conversion device (6) is designed to perform the function of an interpolator, specifically a linear interpolator.
Device according to one of the foregoing claims, characterized in that the second clock-signal generating device (7, 8) is designed in the form of a digital phase-locked loop which includes a digital phase detector device (7) and a digitally controlled oscillator device (8), wherein the digitally controlled oscillator device (8) generates the second clock signal (fT1), and wherein the digital phase detector device (7) determines the phase deviation between the digitized sampling values of the reference signal (FBAS) output by the conversion device (6) and the second clock signal (fT1) generated by the digitally controlled oscillator device (8) and, depending thereon, generates a digital incremental value (INCR) for the digitally controlled oscillator device (8) by which to adjust the frequency of the second clock signal (fT1).
Device according to one of the foregoing claims, characterized in that the operating clock signal (f0) is a high-frequency quartz-coupled clock signal.
Device according to one of the foregoing claims, characterized in that first memory means (2, 3) are provided for temporarily storing the sampling values of the reference signal (FBAS) with the frequency of the second clock signal (fT1) output by the analog-to-digital converter (1), and that second memory means (4, 5) are provided to temporarily store the digital sampling values with the frequency of the first clock signal (fT2) temporarily stored in the first memory means (2, 3), and to feed said sampling values to the conversion device (6).
Device according to one of the foregoing claims, characterized in that a counter (9) operated at the operating clock frequency (f0) is provided, and that the first clock-signal generating device (11) is designed so that the first clock signal (fT2) is generated by evaluating the count of the counter (9).
Device according to one of the foregoing claims, characterized in that the reference signal (FBAS) is a video signal, specifically a television signal, and that the frequency (f0) of the operating clock signal, from which the first and/or second clock signal (fT2;
Dependencies are inferred from the claim text.