Semiconductor integrated circuit equipment with asynchronous operation

A semiconductor integrated circuit device comprising:

• a memory cell array,
• a chip enable transition detecting circuit which detects transition of a chip enable signal which specifies start of an operation of the memory cell array,
• an address transition detecting circuit which detects transition of a row address signal which specifies a row address of the memory cell array and transition of a column address signal which specifies a column address thereof,
• a write enable transition detecting circuit which detects transition of a write enable signal which specifies a write operation of the memory cell array, and
• a control circuit including a timeout circuit which generates an internal circuit control signal with preset width to control access to the memory cell array based on detection results of the chip enable transition detecting circuit, address transition detecting circuit and write enable transition detecting circuit,
• wherein the control circuit controls the operation of the memory cell array by use of the timeout circuit at the time of the read operation with respect to the memory cell array, controls the operation of the memory cell array by use of the timeout circuit when transition of an end of the write enable signal is detected by the write enable transition detecting circuit before a timing specified by the timeout circuit is terminated at the time of the write operation with respect to the memory cell array, and controls the operation of the memory cell array in response to transition of the write enable signal when transition of the end of the write enable signal is detected by the write enable transition detecting circuit after the timing specified by the timeout circuit has elapsed at the time of the write operation with respect to the memory cell array.