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US 2003/0156487 A1Published application
Semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakashi Izutsu, Shigeki Ohbayashi, Yoji Kashihara
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Abstract
During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.
Claims7
A semiconductor memory device, comprising:
- a plurality of memory cells each storing data;
- a plurality of word lines provided corresponding to respective memory cell rows;
- a plurality of bit line pairs provided corresponding to respective memory cell columns, and each being formed with complementary first and second bit lines;
- a write data bus pair formed with complementary first and second write data buses;
- a write control circuit to set said first and second write data buses to one and the other of first and second voltages respectively corresponding to write data when activated;
- a plurality of write selection gates provided corresponding to respective said memory cell columns, and each connecting corresponding ones of said first and second bit lines to said first and second write data buses, respectively, according to a column select result when activated;
- a read data bus pair formed with complementary first and second read data buses;
- a plurality of read selection gates provided corresponding to respective said memory cell columns, and each connecting corresponding ones of said first and second bit lines to said first and second read data buses, respectively, according to a column select result when activated;
- a sense amplifier circuit to amplify a voltage difference between said first and second read data buses when activated;
- a precharge and equalize circuit to set each of said first and second read data buses to a prescribed voltage when activated;
- and
- a control circuit to control activation of said write control circuit, said plurality of write selection gates, said plurality of read selection gates, said sense amplifier circuit, and said precharge and equalize circuit;
- wherein
- said control circuit activates said write control circuit, said plurality of write selection gates, said plurality of read selection gates, and said sense amplifier circuit and inactivates said precharge and equalize circuit, during a test different from a normal operation.
11 more elements
Dependencies are inferred from the claim text.