Fast accessing of a memory device

A memory device comprising:

• an input buffer for receiving a memory address;
• a decoder connected to the input buffer for producing a decoded memory address from the memory address during a setup time of a load path of the memory device;
• and
• a counter connected to the decoder for producing a count value based on the decoded memory address.

A memory device comprising:

• a plurality of input nodes for receiving a memory address;
• a decoder for decoding the memory address during a setup time of a load path for the memory device to generate a decoded memory address;
• a counter connected to the decoder for counting the decoded memory address to generate a count;
• and
• a plurality of write drivers connected to the counter, wherein the counter is configured to activate at least one of the write driver during the setup time.

A memory device comprising:

• a decoder for decoding at least a portion of a column address to generate a decoded address;
• a multiple bit shift register connected to the decoder for generating a count value based on the decoded address;
• and
• a number of write drivers connected to the multiple bit shift register for receiving the count value, wherein the multiple shift register is configured to activate at least one of the write drivers based on the count value during a memory access operation of the memory device.

A memory device comprising:

• an input buffer for receiving a column address;
• a decoder connected to the input buffer for decoding a portion of the column address to generate a decoded address;
• a counter connected to the decoder for generating a count value based on the decoded address;
• a number of write drivers connected to the counter for receiving the count value;
• a column decoder connected to the counter for receiving the column address;
• and
• a memory array connected to the column decoder and the write drivers for receiving data from at least one of the write drivers based on the count value and the column address, wherein the decoder is configured to decode the portion of the column address before the column address is loaded into the column decoder.

A memory device comprising:

• an input buffer for receiving a memory address;
• a decoder connected to the input buffer for decoding a portion of the memory address to generate a decoded address;
• a counter connected to the decoder for generating a count value based on the decoded address, wherein the decoder is configured to generate the decoded address before the memory address is located into the counter;
• a holding circuit connected to the input buffer for holding an encoded version of the address;
• a multiplexor connected to the counter and the holding circuit for receiving the count value and the encoded version of the memory address to determine a completion of a counting by the counter;
• a number of write drivers connected to the counter for receiving the count value;
• and
• a memory array connected to the write drivers, wherein the counter is configured to activate at least one of the write drivers during a memory access operation of the memory device, and the decoder is configured to generate the decoded memory address before the memory address is loaded into the counter.

A system comprising:

• a processing unit;
• and
• a memory device connected to the processing unit, the memory device comprising:
• an input buffer for receiving a memory address;
• a decoder connected to the input buffer for generating a decoded memory address based on the memory address;
• and
• a counter connected to the decoder for generating a count value based on the decoded memory address, wherein the decoder is configured to decode the memory address before the memory address is loaded into the counter.

A system comprising:

• a processing unit;
• and
• a dynamic memory device connected to the processing unit, the dynamic memory device comprising:
• an input buffer for receiving a column address;
• a decoder connected to the input buffer for decoding a portion of the column address to generate a decoded address;
• a counter connected to the decoder for generating a count value based on the decoded address;
• a number of write drivers connected to the counter for receiving the count value;
• a column decoder connected to the counter for receiving the column address;
• and
• a memory array connected to the column decoder and the write drivers for receiving data from at least one of the write drivers based on the count value and the column address, wherein the decoder is configured to decode the portion of the column address before the column address is loaded into the column decoder.

A method of operating a memory device, the method comprising:

• receiving a memory address;
• decoding the memory address to produce decoded memory address;
• producing a count value based on the decoded memory address;
• and
• activating at least one write driver among a plurality of write drivers based on the count value during a setup time of a load path of the memory device.