Method and circuit for repairing nonvolatile ferroelectric memory device

A method of repairing a nonvolatile ferroelectric memory device in a fail row address relieving method, the method comprising the steps of:

• storing fail row addresses in a plurality of redundancy coding cells of a redundancy coding section composed of a ferroelectric capacitor, a redundancy master cell and the redundancy coding cells;
• if input row addresses satisfy conditions encrypted by a user, activating a master signal through the redundancy master cell by outputting to the redundancy coding section a set signal, a reset signal and first to sixth control signals ENN, ENP, EQN<, CPL, ENW<n> and PREC;
• if the input row addresses correspond to the fail row addresses stored in the redundancy coding cells, outputting seventh and eighth control signals REN<n> and RPUL<n> by performing a logical operation of the master signal;
• if the input row addresses correspond to the fail row addresses stored in the redundancy coding section, outputting a ninth control signal DECDIS for inactivating normal input/output paths and a tenth control signal REDEN for activating redundancy input/output paths through the redundancy control section which receives the eighth control signal RPUL<n> as its input;
• and
• inactivating driving of corresponding main cells of a main cell array section and activating driving of corresponding redundancy cells of a redundancy cell array section by the eighth to tenth control signals REN<n>, DECDIS and REDEN.

A method of repairing a nonvolatile ferroelectric memory device in a fail column address relieving method, the method comprising the steps of:

• storing fail column addresses in a plurality of redundancy coding cells of a redundancy coding section composed of a ferroelectric capacitor, a redundancy master cell and the redundancy coding cells, and storing fail input/output numbers FION<r> which indicate input/output lines corresponding to the fail column addresses in redundancy input/output coding cells of a redundancy input/output coding section composed of a ferroelectric capacitor, and the redundancy input/output coding cells;
• if input column addresses satisfy conditions programmed by a user, activating a master signal through the redundancy master cell by outputting to the redundancy coding section a set signal, a reset signal and first to sixth control signals ENN, ENP, EQN<, CPL, ENW<n> and PREC;
• if the input column addresses correspond to the fail column addresses stored in the redundancy coding cells, outputting a seventh control signal RPUL<n> by performing a logical operation of the master signal;
• outputting an eighth control signal DECDIS and a redundancy read/write mode control signal WLRHR for activating driving of the redundancy cells through a redundancy control section which receives the read/write mode control signal WLRH and the seventh control signal RPUL<n> as its inputs;
• and
• inactivating driving of normal input/output paths by receiving the eighth control signal DECDIS and activating driving of redundancy input/output paths corresponding to the inactivated normal input/output paths by receiving the redundancy read/write mode control signal WLRHR.

A circuit for repairing a nonvolatile ferroelectric memory device comprising:

• an address latch for maintaining and outputting input row addresses for one period;
• a state diagram generating section for outputting first to sixth control signals ENN, ENP, EQN, ENW<n>, CPL and PREC for activating a fail relieving operation, a set signal and a reset signal if the input row addresses satisfy conditions encrypted by a user;
• and
• a programmable redundancy coding section for activating a master signal by receiving the first to sixth control signals ENN, ENP, EQN, ENW<n>, CPL and PREC, the set signal and the reset signal, storing fail row address in a plurality of redundancy coding cells, and if the input row addresses correspond to the stored fail row addresses, outputting seventh to tenth control signals REN<n>, RPUL<n>, DECDIS and RENEN for inactivating normal data input/output paths and activating data input/output paths which can be used as redundancy paths.

A circuit for repairing a nonvolatile ferroelectric memory device comprising:

• an address latch for maintaining and outputting input column addresses for one period;
• a state diagram generating section for generating first to sixth control signals ENN, ENP, EQN, CPL, ENW<n> and PREC for activating a fail relieving operation, a set signal, a reset signal and pulses of fail input/output (IO) numbers FION<r> if the input column addresses satisfy conditions encrypted by a user;
• a programmable redundancy coding section for receiving an eighth control signal WLRH for controlling an operation of a main amplifier, the first to sixth control signals ENN, ENP, EQN, CPL, ENW<n> and PREC, the set signal and the reset signal, and outputting a seventh control signal RPUL<n>, a ninth control signal WLRHR for controlling an operation of a redundancy amplifier, and a tenth control signal RIODIS for controlling an input/output for a normal operation;
• a redundancy IO multiplexer coding section for storing the first to fifth control signals ENN, ENP, EQN, CPL and ENW<n> and fail IO numbers FION<r>, and connecting data input/output to main input/output MIO<r> or redundancy input/output RIO<q> under the control of the seventh control signal RPUL<n>;
• and
• a normal IO path section for receiving the tenth control signal RIODIS and connecting the data input/output to the main input/output MIO<r>.