Semiconductor integrated circuit device

Abstract

There is provided a semiconductor integrated circuit device which can select the cache memory operation as required in which the priority is given to high speed operation or to low power consumption. In this circuit device, a set associative type cache memory includes read amplifier units for data-ways to provide a first operation mode for selecting an output from the data-way in relation to the cache hit state through the activation by giving limitation only to the read amplifier unit of the data-way in relation to the cache bit and a second operation mode for selecting an output from the data-way in relation to the cache hit without limitation on the read amplifiers to be activated. Selection of above operation mode is programmable depending on the setting of mode bit.

Dependencies are inferred from the claim text.