Physically alternating sense amplifier activation
AssigneeMicron Technology, Inc.
InventorJohn Schreck
Life of this patent
Estimating the term…
Abstract
A memory device having banks of sense amplifiers comprising two types of sense amplifiers. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.
Claims43
A memory device comprising:
- first and second banks of sense amplifiers, each sense amplifier comprising a first type of sense amplifier and a second type of sense amplifier, said first bank of sense amplifiers including at least one first driver circuit for activating said first type of sense amplifier in said first and second banks, and said second bank of sense amplifiers including at least one second driver circuit for activating said second type of sense amplifier in said first and second banks.
A memory device comprising:
- a plurality of memory cells organized into sub-arrays;
- and
- a plurality of first and second banks of sense amplifiers for latching and amplifying memory cells in said sub-arrays, each sense amplifier comprising a first type of sense amplifier and a second type of sense amplifier, each first bank of sense amplifiers including at least one first driver circuit for activating said first type of sense amplifier in said first bank, each second bank of sense amplifiers including at least one second driver circuit for activating said second type of sense amplifier in said second bank, and
- wherein said plurality of first and second banks are physically alternated in a horizontal direction throughout said device.
A processor system comprising:
- a processor;
- and
- a memory circuit coupled to said processor, said memory circuit comprising:
- first and second banks of sense amplifiers, each sense amplifier comprising a first type of sense amplifier and a second type of sense amplifier, said first bank of sense amplifiers including at least one first driver circuit for activating said first type of sense amplifier in said first and second banks, and said second bank of sense amplifiers including at least one second driver circuit for activating said second type of sense amplifier in said first and second banks.
A processor system comprising:
- a processor;
- and
- a memory device integrated with an coupled to said processor, said memory device comprising:
- a plurality of memory cells organized into sub-arrays;
- and
- a plurality of first and second banks of sense amplifiers for latching and amplifying memory cells in said sub-arrays, each sense amplifier comprising a first type of sense amplifier and a second type of sense amplifier, each first bank of sense amplifiers including at least one first driver circuit for activating said first type of sense amplifier in said first bank, each second bank of sense amplifiers including at least one second driver circuit for activating said second type of sense amplifier in said second bank, and
- wherein said plurality of first and second banks are physically alternated in a horizontal direction throughout said device.
Dependencies are inferred from the claim text.