Semiconductor memory device operating in synchronization with clock signal

A semiconductor memory device capturing an address signal in response to a leading edge of a clock signal comprising:

• plural memory cells;
• a select circuit selecting a memory cell of said plural memory cells according to an address signal;
• a write/read circuit performing writing/reading of a data signal to/from the memory cell selected by said select circuit;
• and
• a coincidence/non-coincidence detecting circuit detecting whether or not inputted two address signals coincide with each other to output a control signal controlling said write/read circuit on the basis of a result of the detection, wherein
• said coincidence/non-coincidence detecting circuit includes:
• a charge circuit for charging a prescribed node to a first potential;
• plural discharge circuits provided correspondingly to respective plural signals included in an address signal, and each receiving respective corresponding two signals included in inputted two address signals to discharge said prescribed node to a second potential in response to a situation where two signals that each discharge circuit has received are different from each other in logical level;
• and
• a signal generating circuit generating said control signal on the basis of a potential of said prescribed node.