Programmable conductor random access memory and method for sensing same

A method for reading a semiconductor memory cell, the method comprising:

• setting a voltage of a cell plate of said cell, to which a first portion of a resistive element of said cell is coupled, to a first predetermined voltage;
• charging a first terminal of an access transistor of said cell and a reference conductor to a second predetermined voltage, wherein said first terminal is coupled to a column line of said cell, wherein a second terminal of said transistor is coupled to a second portion of said resistive element, and wherein said first terminal and said reference conductor are coupled to respective inputs of a comparator;
• charging a gate of said access transistor to a third predetermined voltage in order to read said cell, wherein said gate is coupled to a rowline of said cell;
• discharging said first terminal from said second predetermined voltage through the resistive element;
• and
• comparing a voltage at said first terminal with said second predetermined voltage a predetermined period of time after said act of discharging begins in order to determine a logical state of said cell.

A method for sensing a stored value of a programmable conductor random assess memory cell, the method comprising:

• precharging a digit line coupled to a first terminal of an access transistor of said cell to a first predetermined voltage;
• charging a cell plate of said cell to a second predetermined voltage, said second predetermined voltage being a value between 0V and said first predetermined voltage;
• and
• applying a third predetermined voltage to a rowline coupled to a gate of said access transistor such that a resulting voltage across said programmable conductor memory cell is sufficient to read a logical state of said cell, but insufficient to program said cell.

A method for sensing a stored value of a programmable conductor random access memory cell, the method comprising:

• precharging a digit line to a reference voltage value, said digit line being coupled to a first terminal of an access transistor of said cell;
• charging a cell plate of said cell to a first predetermined voltage, said first predetermined voltage being a value between 0V and said reference voltage value;
• firing a rowline of said memory cell by applying a second predetermined voltage, said second predetermined voltage being sufficient to read said memory cell, but insufficient to program said memory cell;
• and
• comparing a voltage read at said digit line with said reference voltage in order to determine a logical state of said memory cell.

A semiconductor memory structure comprising:

• a digit line and a digit complement line;
• a circuit for precharging said digit line and said digit complement line to a predetermined voltage value prior to a read operation;
• an access transistor for coupling a programmable conductor memory element to said digit line during a read operation;
• and
• a sense amplifier for comparing voltages on said digit line and said digit complement line during said read operation to determine a logical state of said memory element.

A semiconductor memory comprising:

• a programmable conductor memory element;
• a column line;
• a rowline;
• a conductor for applying a first voltage to a first terminal of said programmable conductor memory element;
• a transistor for selectively coupling said column line to another terminal of said programmable conductor memory element in response to a gate voltage applied to said rowline;
• a sense amplifier coupled to said column line and a reference conductor;
• and
• a precharge circuit for precharging said column line and reference conductor to a predetermined voltage prior to application of a gate voltage to said rowline,
• said sense amplifier comparing a voltage on said column line and reference line to determine a resistance value of said programmable conductor memory element after said gate voltage is applied to said rowline.

A processor system, comprising:

• a processor;
• and
• a semiconductor memory structure coupled to said processor, said semiconductor memory structure comprising:
• a digit line and a digit complement line;
• a circuit for precharging said digit line and said digit complement line to a predetermined voltage value prior to a read operation;
• an access transistor for coupling a programmable conductor memory element to said digit line during a read operation;
• and
• a sense amplifier for comparing voltages on said digit line and said digit complement line during said read operation to determine a logical state of said memory element.

A processor system comprising:

• a processor;
• and
• a semiconductor memory coupled to said processor, said semiconductor memory comprising:
• a programmable conductor memory element;
• a column line;
• a rowline;
• a conductor for applying a first voltage to a first terminal of said programmable conductor memory element;
• a transistor for selectively coupling said column line to another terminal of said programmable conductor memory element in response to a gate voltage applied to said rowline;
• a sense amplifier coupled to said column line and a reference conductor;
• and
• a precharge circuit for precharging said column line and reference conductor to a predetermined voltage prior to application of a gate voltage to said rowline,
• said sense amplifier comparing a voltage on said column line and reference line to determine a resistance value of said programmable conductor memory element after said gate voltage is applied to said rowline.