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US 2003/0156462 A1Published application
Memory devices having power supply routing for delay locked loops that counteracts power noise effects
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun-Wook Lim, Dae-Hyun Chung
Life of this patent
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Abstract
A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.
Claims19
A memory device, comprising:
- first and second power supply pads configured to be connected to a power supply;
- a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal;
- and
- a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.
1 more element
A semiconductor memory device comprising:
- a data output path that receives an internal clock and data to be output and that synchronizes the data to the internal clock and outputs the synchronized data;
- and
- a delay locked loop (DLL) that receives an external clock and generates the internal clock, the DLL including a variable delay line which delays the internal clock with respect to the external clock in response to a delay control signal and DLL peripheral circuitry that generates the delay control signal from the external clock and a feedback clock that is derived from the internal clock and compensated for delay time of a data output circuit of the data output path,
- wherein the variable delay line receives dedicated power for the variable delay line, and
- the DLL peripheral circuitry receives dedicated power for the DLL peripheral circuitry.
2 more elements
A semiconductor memory device comprising:
- a data output path that receives an internal clock and data to be output and that synchronizes the data to the internal clock and outputs the synchronized data;
- a DLL that receives an external clock and generates the internal clock therefrom, the DLL including a variable delay line that delays the internal clock with respect to the external clock in response to a delay control signal, and DLL peripheral circuitry that generates the delay control signal from the external clock and a feedback clock that is derived from the internal clock compensated for a delay time of a data output circuit of the data output path;
- a general-purpose power pad that receives general-purpose power to supply the general-purpose power to the data output path;
- a variable delay line power pad that receives dedicated power for variable delay line so as to supply the power to the variable delay line;
- and
- a peripheral circuitry power pad that receives dedicated power for peripheral circuitry so as to supply the power to the DLL peripheral circuitry.
3 more elements
Dependencies are inferred from the claim text.