Method and apparatus for simultaneous differential data sensing and capture in a high speed memory
AssigneeMosaid Technologies Incorporated
InventorPaul Demone
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Abstract
A differential data sensing and capture circuit, includes a differential input stage circuit for receiving respective ones of said differential data signals and having first and second output nodes. A latch element is provided, having first and second complementary inputs coupled to receive signals from said respective first and second output nodes. A gating circuit dynamically enables and disables a clock signal to the differential input stage in response to an enable signal, such that power consumption in said differential input stage is conserved. In a further embodiment the enable signal is a complementary clock input signal.
Claims5
A differential input latch for use in a semiconductor memory, comprising:
- (a) a differential input stage circuit for receiving respective ones of a pair of input data signals to generate a pair of output signals at respective first and second nodes, indicative of a difference between said pair of input data signals;
- (b) an amplifying element for amplifying said output signals at said first and second nodes;
- (c) a latch element for latching said respective amplified output signals at said first and second output nodes;
- and
- (d) a gating circuit for dynamically enabling and disabling a clock signal to said differential input stage in response to an enable signal, such that power consumption in said differential input stage is conserved.
A method for differential data sensing and capture, comprising the steps of:
- (a) receiving at a differential input stage circuit respective ones of said differential data signals, said differential input stage having first and second output nodes;
- (b) amplifying said first and second output nodes;
- (c) coupling said amplified first and second output nodes to a latch element having first and second complementary inputs;
- (d) selectively enabling and disabling a clock signal to said differential input stage in response to an enable signal, such that power consumption in said differential input stage is conserved.
A differential input latch for use in a semiconductor memory, comprising:
- (a) a differential input stage circuit for receiving respective ones of a pair of input data signals to generate a pair of output signals at respective first and second nodes, indicative of a difference between said pair of input data signals;
- (b) an amplifying element for amplifying said output signals at said first and second nodes;
- (c) a latch element for latching said respective amplified output signals at said first and second output nodes;
- and
- (d) a clock input node associated with said differential input stage for dynamically enabling and disabling said differential input stage in response to an enable signal, such that power consumption in said differential input stage is conserved.
Dependencies are inferred from the claim text.