Self-aligned split-gate flash memory cell and its contactless memory array

A self-aligned split-gate flash memory array with a circuit configuration comprising:

• a plurality of common-source conductive bus lines and a plurality of common-drain conductive bus lines being formed in parallel and alternately;
• a plurality of self-aligned split-gate flash memory cells being formed between said common-source conductive bus line and said common-drain conductive bus line, wherein said common-source/drain conductive bus line is electrically connected with common-source/drain diffusion regions of said self-aligned split-gate flash memory cells in each column, and each of said self-aligned split-gate flash memory cells comprises a floating-gate transistor being faced to said common-source conductive bus line and a select-gate transistor being faced to said common-drain conductive bus line;
• and
• a plurality of word lines being formed transversely to the plurality of common-source/drain bus lines, wherein each of the plurality of word lines is connected with a plurality of control-gates of said self-aligned split-gate flash memory cells in each row.

A contactless self-aligned split-gate flash memory array, comprising

• a semiconductor substrate of a first conductivity type;
• a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein each of the plurality of parallel STI regions is filled with a raised field-oxide layer and each of the plurality of active regions is filled with a floating-gate layer being formed over a thin tunneling-dielectric layer;
• a plurality of virtual gate regions and a plurality of common-source bus-line regions being formed alternately over said semiconductor substrate and transversely to the plurality of parallel STI regions, wherein the plurality of virtual gate regions are patterned by a masking photoresist step and are therefore scalable;
• a plurality of common-source diffusion regions of a second conductivity type being formed by implanting doping impurities in a self-aligned manner into said semiconductor substrate of the plurality of active regions along the plurality of common-source bus-line regions;
• a first flat bed being formed in each of the plurality of common-source bus-line regions and being alternately formed by said common-source diffusion region and a first etched raised field-oxide layer, wherein a pair of first sidewall dielectric spacers are separately formed over each sidewall of nearby said virtual gate regions and on a portion of said first flat bed, and each of the plurality of common-source bus-line regions comprises from top to bottom a first planarized thick-oxide layer being formed over said pair of first sidewall dielectric spacers and a common-source conductive bus line being formed over said first flat bed between said pair of first sidewall dielectric spacers;
• a self-aligned split-gate region being formed in each side portion of said virtual gate region and a common-drain region being formed between said self-aligned split-gate regions, wherein said self-aligned split-gate region is defined by a fourth sidewall dielectric spacer being formed over a sidewall of said common-source bus-line region and is divided into two subregions:
• a floating-gate region being formed near said common-source bus-line region and a select-gate region being formed near said common-drain region, and said floating-gate region comprises a plurality of floating-gate transistors with each of the plurality of floating-gate transistors being formed on said thin tunneling-dielectric layer and said select-gate region comprises a plurality of select-gate transistors with each of the plurality of select-gate transistors being formed on a gate-dielectric layer;
• a second flat bed being formed in each of the plurality of common-drain regions and being alternately formed by said common-drain diffusion region and a second etched raised field-oxide layer, wherein a pair of second sidewall dielectric spacers are formed over each sidewall of nearby said self-aligned split-gate regions and on a portion of said second flat bed, and each of the plurality of common-drain regions comprises from top to bottom a second planarized thick-oxide layer being formed over said pair of second sidewall dielectric spacers and a common-drain conductive bus line being formed over said second flat bed between said pair of second sidewall dielectric spacers;
• and
• a plurality of word lines being formed alternately above the plurality of active regions and transversely to the plurality of common-source/drain conductive bus lines and being electrically connected with said planarized control-gates along the plurality of active regions, wherein each of the plurality of word lines is formed by a metal layer together with said planarized control gates being simultaneously patterned and etched by a masking dielectric layer being located above said active region and its two sidewall dielectric spacers.