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US 2003/0156457 A1Published application
Memory device trapping charges in insulating film to store information in non-volatile manner
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
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Abstract
Dummy cells in an erased state and in a write state are used to generate a dummy current corresponding to the average current of currents flowing in the dummy cells using a ½ current generating circuit, and the dummy current is compared with a current corresponding to a memory cell current flowing in a selected normal cell using a current sense amplification circuit to generate internal read data according to a result of the comparison. With such a configuration, a non-volatile semiconductor memory device capable of reading data at high speed can be achieved.
Claims19
A non-volatile semiconductor memory device comprising:
- a plurality of non-volatile memory cells, arranged in rows and columns, each storing data in a non-volatile manner and including an insulated gate transistor having a threshold voltage set according to stored data, said threshold voltage having at least a first state corresponding to a data at a first logical level and a second state corresponding to data at a second logical level;
- a plurality of bit lines provided corresponding to the memory cell columns, and connected to the memory cells on corresponding columns;
- read current generating circuitry for supplying a current to a bit line of a selected column, in data reading;
- reference current generating circuitry for generating a reference current, said reference current, with respect to a read current flowing from said read current generating circuitry into the bit line of the selected column, having a magnitude of an average of a first read current corresponding to a current flowing through said bit line of the selected column from said read current generating circuitry when a memory cell in said first state is selected and a second read current corresponding to a current flowing through said bit line of the selected column from said read current generating circuitry when a memory cell in said second state is selected;
- comparison circuitry for comparing the reference current from said reference current generating circuitry with the current from said read current generating circuit to generate an output signal corresponding to a result of comparison;
- and
- internal read circuitry for generating internal read data according to the output signal of said comparison circuit.
4 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of non-volatile memory cells, arranged in rows and columns, each storing data in a non-volatile manner and each including an insulated gate transistor having a threshold voltage set according to stored data, the threshold voltage including at least a first threshold voltage corresponding to stored data at a first logical level and a second threshold voltage corresponding to stored data at a second logical level;
- a plurality of bit lines, provided corresponding to the memory cell columns, each connected to the memory cells on a corresponding column;
- and
- reference current generating circuitry for generating a reference current, said reference current, in data reading, having a magnitude of an average of a first current flowing through a memory cell having said first threshold voltage when said memory cell having said first threshold voltage is selected and a second current flowing through a memory cell having said second threshold voltage when said memory cell having said second threshold voltage is selected;
- constant current generating circuitry for generating a constant current having a prescribed magnitude;
- comparison circuitry for supplying said constant current into a bit line of a selected column as a read current and generating an output signal corresponding to a difference between said read current and said reference current;
- and
- internal read circuitry for generating internal read data according to the output signal of said comparison circuitry.
5 more elements
A non-volatile semiconductor memory device comprising:
- plural memory cells, arranged in rows and columns, each including a memory transistor having a threshold voltage changing according to stored data;
- a plurality of bit lines, provided corresponding to the memory cell columns, each connected to the memory cells on a corresponding column;
- a read current supply current circuitry for supplying a current into the bit line of a selected column;
- reference current generating circuitry for generating a reference current;
- and
- current comparison circuitry for comparing a current flowing through a selected memory cell on the selected column with said reference current and generating a signal indicating a result of comparison.
3 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of non-volatile memory cells, arranged in rows and columns, each storing information in a non-volatile manner and each including a transistor having a threshold voltage set according to stored information;
- a plurality of bit lines, provided corresponding to the columns and connected to memory cells on corresponding columns, each shared between the memory cells on adjacent columns;
- current supply circuitry coupled to a first bit line of a selected column, for supplying a current into said first bit line;
- and
- a sense amplifier coupled to a second bit line of said selected column, for generating internal read data according to a current flowing through said second bit line.
2 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of non-volatile memory cells, arranged in rows and columns, each storing information in a non-volatile manner and each including a transistor having a threshold voltage set according to stored information;
- a plurality of bit lines, provided corresponding to the columns and connected to the memory cells on corresponding columns, each shared between the memory cells on adjacent columns;
- current supply circuitry coupled to a first bit line of a selected column, for supplying a current into the first bit line;
- reference power supply coupled to a second bit line of said selected column;
- and
- a sense amplifier coupled to said first bit line in parallel to said current supply circuitry, for generating internal read data according to a supplied current in data reading.
3 more elements
Dependencies are inferred from the claim text.