Semiconductor integrated circuit adapted to output pass/fail results of internal operations
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Claims28
A semiconductor integrated circuit comprising:
- an internal circuit configured to execute a first operation and a second operation concurrently;
- and
- an output circuit connected to the internal circuit, the output circuit configured to output to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
A semiconductor integrated circuit comprising:
- a PASS/FAIL decision circuit configured to decide a result of an immediately preceding operation and output a PASS/FAIL signal;
- a PASS/FAIL holding circuit connected to receive the pass/fail signal for holding separately the pass/fail result of each of first and second operations which are performed successively;
- and
- an output circuit configured to output the pass/fail result of each of the first and second operations held in the pass/fail holding circuit when the first and second operations are performed successively.
A semiconductor integrated circuit comprising:
- a plurality of data cache circuits connected to data input/output lines, the plurality of data cache circuits configured to hold data temporarily;
- and
- a plurality of sense latch circuits connected to the plurality of data cache circuits, the plurality of sense latch circuit configured to sense and latch data read from memory cells and latching data to be programmed into memory cells.
An operating method of a semiconductor integrated circuit comprising:
- performing a first operation and a second operation in succession;
- internally holding a pass/fail result of the first operation after the termination thereof;
- internally holding a pass/fail result of the second operation after the termination thereof;
- and
- outputting to the outside of the semiconductor integrated circuit both the pass/fail result of the first operation and the pass/fail result of the second operation after the termination of the first and second operations.
An operating method of a semiconductor integrated circuit executing a first operation and a second operation concurrently, comprising:
- outputting to the outside of the semiconductor integrated circuit first information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Dependencies are inferred from the claim text.