Direct memory swapping between NAND flash and SRAM with error correction coding

A memory system for a wireless communication device, comprising:

• a static random access memory (SRAM) storage unit operative to provide storage of data;
• a NAND Flash storage unit operative to provide additional storage of data;
• an interface unit implemented within an application specific integrated circuit (ASIC) and operative to provide control signals for the SRAM and NAND Flash storage units;
• and
• a data bus coupled to the SRAM and NAND Flash storage units and the interface unit, wherein the SRAM and NAND Flash storage units are implemented external to the ASIC, and wherein each storage unit is operable to concurrently store data from the other storage unit via the data bus when the other storage unit is accessed by the interface unit.

A wireless communication device comprising:

• an external memory unit including a static random access memory (SRAM) storage unit operative to provide storage of data and a NAND Flash storage unit operative to provide additional storage of data;
• an application specific integrated circuit (ASIC) including an interface unit operative to provide control signals for the SRAM and NAND Flash storage units;
• and
• a data bus coupled to the SRAM and NAND Flash storage units and the interface unit, wherein the SRAM and NAND Flash storage units are each operable to concurrently store data from the other storage unit via the data bus when the other storage unit is accessed by the interface unit.

An apparatus comprising:

• first means for providing volatile storage of data;
• second means for providing non-volatile storage of data;
• third means for providing control signals to effectuate data transfers between the first and second means;
• and
• means for interconnecting the first, second, and third means, wherein the third means is implemented within an application specific integrated circuit (ASIC) and the first and second means are implemented external to the ASIC, and wherein each of the first and second means is operable to concurrently store data from the other means via the interconnecting means when the other means is accessed by the third means.

A method for transferring data between two storage units in a wireless communication device, comprising:

• receiving a start address for an SRAM storage unit;
• receiving a page address for a NAND Flash storage unit;
• providing control signals for the SRAM and NAND Flash storage units in response to receiving a start command;
• retrieving data from a source storage unit via a data bus, wherein the source storage unit is either the SRAM or NAND Flash storage unit;
• and
• writing the retrieved data to a destination storage unit via the data bus concurrently with the reading of the data from the source storage unit, wherein the destination storage unit is the other storage unit that is not the source storage unit.

A memory communicatively coupled to a digital signal processing device (DSPD) capable of interpreting digital information to:

• receive a start address for an SRAM storage unit;
• receive a page address for a NAND Flash storage unit;
• receive a start command for a page transfer operation;
• provide control signals for the SRAM and NAND Flash storage units in response to the start command;
• retrieve data from a source storage unit via a data bus, wherein the source storage unit is either the SRAM or NAND Flash storage unit;
• and
• write the retrieved data to a destination storage unit via the data bus concurrently with the reading of the data from the source storage unit, wherein the destination storage unit is the other storage unit that is not the source storage unit.