Integrated memory and method for operating an integrated memory
AssigneeInfineon Technologies AG
InventorPeter Pochmuller
Life of this patent
Estimating the term…
Abstract
An integrated memory includes memory cells arranged in a memory cell array and a read/write amplifier for evaluating and amplifying data signals of the memory cells that are being read out or written to. An error correction circuit is connected to the read/write amplifier. Data signals of selected memory cells that are to be read out or written are received by the error correction circuit, checked for errors, and in the case of a detected erroneous data signal, the erroneous data signal is corrected by being inverted and is output. The memory, even in the case of a defective memory cell, in particular a memory cell with a variable memory cell time or retention time (also called VRT-Variable Retention Time), can nevertheless largely be operated reliably.
Claims19
An integrated memory, comprising:
- a memory cell array including a plurality of memory cells;
- a read/write amplifier for evaluating and amplifying data signals being read out from or written to said plurality of memory cells of said memory cell array;
- and
- an error correction circuit connected to said read/write amplifier;
- said error correction circuit capable of being activated when reading out from or writing to said memory cell array;
- said error correction circuit for receiving and checking the data signals, being read out from or written to said memory cell array, for errors;
- and
- said error correction circuit, upon detecting an erroneous data signal, correcting the erroneous data signal by inverting the erroneous data signal and outputting a corrected data signal.
A method for operating an integrated memory, which comprises:
- providing a memory cell array including a plurality of memory cells;
- providing a read/write amplifier for evaluating and amplifying data signals being written to or read out from the plurality of memory cells;
- connecting an error correction circuit to the read/write amplifier;
- providing the error correction circuit with data signals of selected memory cells that are being written to or read out from;
- and
- in the error correction circuit, checking the data signals for errors, and when detecting an erroneous data signal, correcting the erroneous data signal by inverting the erroneous data signal and outputting a corrected data signal.
Dependencies are inferred from the claim text.