Multiple data state memory cell
AssigneeMicron Technology, Inc.
InventorTerry L. Gilton
Life of this patent
Estimating the term…
Abstract
A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.
Claims56
A multiple-state memory cell, comprising:
- a first electrode layer formed from a first conductive material;
- a second electrode layer formed from a second conductive material;
- a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers, the first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers;
- a third electrode layer formed from a third conductive material;
- and
- a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.
A multiple-state memory cell, comprising:
- a first electrode coupled to a first voltage;
- a second electrode coupled to a second voltage;
- a multiple layer data state stack in which multiple data states are stored, the data-state stack including:
- a first portion of a metal-doped chalcogenide material adjoining the first electrode, the first portion having a first thickness;
- a third electrode of a conductive material adjoining the first portion;
- and
- a second portion of a metal-doped chalcogenide material adjoining the third electrode, the second portion having a second thickness,
- wherein application of a programming voltage to the first electrode induces the formation of a first conductive growth from the third electrode to the first electrode and a second conductive growth from the second electrode to the third electrode.
A multiple state memory cell, comprising:
- a first electrode layer formed from a first conductive material;
- a second electrode layer formed from a second conductive material;
- a first layer of a metal-doped chalcogenide material disposed between and adjoining the first and second electrode layers, the first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers;
- a third electrode layer formed from a third conductive material;
- a second layer of a metal-doped chalcogenide material disposed between and adjoining the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers;
- a fourth electrode layer formed from a fourth conductive material;
- and
- a third layer of a metal-doped chalcogenide material disposed between and adjoining the third and fourth electrode layers, the third layer providing a medium in which a conductive growth can be formed to electrically couple together the third and fourth electrode layers.
A memory device, comprising:
- a memory array comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a first electrode layer formed from a first conductive material and coupled to a respective row;
- a second electrode layer formed from a second conductive material;
- a first layer of a metal-doped chalcogenide material disposed between and adjoining the first and second electrode layers, the first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers;
- a third electrode layer formed from a third conductive material and coupled to a respective column;
- and
- a second layer of a metal-doped chalcogenide material disposed between and adjoining the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers;
- a row address decoder for selecting a row of memory cells corresponding to a row address;
- a column address decoder for selecting a column of memory cells corresponding to a column address;
- reading and writing circuitry coupled to the memory array to read data from and write data to the memory cells selected by the row and column address decoders;
- a data path coupled between the reading and writing circuitry and an external data terminal of the memory device;
- and
- a command decoder operable to generate control signals responsive to memory commands applied to the memory device.
A memory device, comprising:
- a memory array comprising a plurality of memory cells arranged in rows and columns, the memory cells comprising:
- a first electrode coupled a respective row;
- a second electrode coupled to a respective column;
- a multiple layer data state stack in which multiple data states are stored, the data-state stack including:
- a first layer of a metal-doped chalcogenide material adjoining the first electrode, the first layer having a first thickness;
- a third electrode layer of a conductive material adjoining the first layer;
- and
- a second layer of a metal-doped chalcogenide material adjoining the third electrode layer, the second layer having a second thickness,
- wherein application of a programming voltage to the first electrode induces the formation of a first conductive growth from the third electrode layer to the first electrode and a second conductive growth from the second electrode too the third electrode layer;
- a row address decoder for selecting a row of memory cells corresponding to a row address;
- a column address decoder for selecting a column of memory cells corresponding to a column address;
- reading and writing circuitry coupled to the memory array to read data from and write data to the memory cells selected by the row and column address decoders;
- a data path coupled between the reading and writing circuitry and an external data terminal of the memory device;
- and
- a command decoder operable to generate control signals responsive to memory commands applied to the memory device.
A method of storing multiple data states in a memory, comprising:
- to store a first data state, short circuiting a first electrode to a second electrode to change a resistance from an initial resistance to a first resistance;
- to store a second data state, short circuiting the second electrode to a third electrode to change the first resistance to a second resistance;
- and
- to store a third data state, substantially maintaining the initial resistance between the first and second electrodes and the second and third electrodes.
A method for forming a multiple state memory cell, comprising:
- forming a first electrode layer from a first conductive material;
- forming a first layer from a metal-doped chalcogenide material on the first electrode layer,
- forming a second electrode layer from a second conductive material on the first layer;
- forming a second layer from a metal-doped chalcogenide material on the second electrode layer;
- and
- forming a third electrode layer from a third conductive material on the second layer,
- the first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers and the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.
Dependencies are inferred from the claim text.