Integrated memory circuit having storage capacitors which can be written to via word lines and bit lines

An integrated memory circuit, comprising:

• word lines including a first word line and a second word line;
• bit lines including a first bit line and a second bit line;
• an address decoding circuit connected to said word lines;
• a read/write amplifier, said bit lines connected in pairs to said read/write amplifier;
• and
• storage capacitors, including a first storage capacitor and a second storage capacitor, coupled to and addressed by said word lines and said bit lines;
• said address decoding circuit activating said first and second word lines during a read and/or write operation, in which case during a write operation of writing a datum, said read/write amplifier being driven so that, through said first bit line, said first storage capacitor addressed by said first word line being occupied by a first charge and, through said second bit line, said second storage capacitor addressed by said second word line being occupied by a second charge, the first charge and the second charge depending on the datum to be written, during a read operation, the first charge of said first storage capacitor flows onto said first bit line and the second charge of said second storage capacitor flows onto said second bit line, the datum to be read out being determined by a charge difference between said first and second bit lines, the charge difference being detected by said read/write amplifier.