Loading patent…
AssigneeHitachi, Ltd.
InventorsNobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
Estimating the term…
An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
A method of data transmission of a data processing apparatus which comprises a microprocessor having data width of m bits (wherein m is an integer), a plurality of memory chips connected to said microprocessor, each of said memory chips having data width of n bits (wherein n is an integer, and m is integer times n), and said plurality of memory chips is divided into two groups, and memory chips of each said groups are mounted on different substrate surfaces, said method comprising the steps of:
A method of data transmission of a data processing apparatus which comprises a microprocessor having data width of m bits (wherein m is an integer), a plurality of memory chips connected to said microprocessor, each of said memory chips having data width of n bits (wherein n is an integer, and m is an integer times n), and said plurality of memory chips is divided into two groups, and memory chips of each said group are mounted on different substrate surfaces, said method comprising the steps of:
A data processing apparatus, comprising:
A method of data transmission of data processing apparatus which comprises a microprocessor for processing data, a semiconductor chip module including a substrate and a plurality of memory chips having data width of n bit data (wherein n is an integer, and m is an integer times n) formed on each side of said substrate, data lines connected to said microprocessor and said plurality of memory chips for slicing m bit data into n bit data and providing said sliced n bit data to each memory chip, said method comprising the steps of:
Dependencies are inferred from the claim text.