Plasma display panel driving method

A method for driving a plasma display panel (PDP), wherein the PDP includes a first electrode and a second electrode respectively formed in parallel on an upper substrate, an address electrode formed normal to the first electrode and the second electrode on a lower substrate, comprising steps of:

• during a reset period,
• applying to the second electrode a first falling ramp voltage gradually decreasing from a first voltage level to a second voltage level, while keeping the first electrode at the first voltage level;
• applying to the second electrode a first rising ramp voltage gradually increasing to a third voltage level, while keeping the first electrode at a fourth voltage level;
• applying to the second electrode a second falling ramp voltage gradually decreasing to a fifth voltage level, while applying to the first electrode a sixth voltage level;
• and
• keeping the address electrode at a seventh voltage level throughout the reset period,
• wherein the fifth voltage level has a negative polarity.

A plasma display panel (PDP), comprising:

• an upper substrate;
• a first electrode and a second electrode formed in parallel on the upper substrate;
• a lower substrate;
• an address electrode;
• and
• a driving circuit that sends a driving signal to the first electrode, the second electrode and the address electrode during a reset period, an address period and a sustain period,
• wherein, during the reset period, the driving circuit,
• applies to the first electrode a first rising ramp voltage gradually increasing to a first voltage level, while keeping the second electrode at the second voltage level;
• applies to the second electrode a second rising ramp voltage gradually increasing to a third voltage level, while keeping the first electrode at a fourth voltage level;
• applies to the second electrode a failing ramp voltage gradually decreasing to a fifth voltage level, while applying to the first electrode a sixth voltage level;
• and
• keeping the address electrode at a ninth voltage level throughout the reset period,
• wherein the fifth voltage level has a negative polarity.