Phase locked loop (PLL)
AssigneeSTMicroelectronics Pvt.Ltd.
InventorSaudas Dey
Life of this patent
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Abstract
An improved phase locked loop (PLL) includes a frequency multiplier and a voltage controlled oscillator (VCO). The VCO includes a control circuit for automatically adjusting its initial free-running frequency in response to changes in an integer divider value. The adjusting is done so that the frequency difference between the initial free-running frequency divided by the integer divider value and a reference frequency is maintained at an approximately constant value. This results in a controllable lock time that is independent of the integer divider value.
Claims12
An improved phase locked loop (PLL) comprising:
- a frequency multiplier including a Voltage Controlled Oscillator (VCO) and having one input connected to a reference frequency signal,
- its second input connected to a programmable frequency divider network, programmable for dividing an input frequency by an integer value ‘N’, and
- its output connected to the input of said programmable frequency divider network while producing an output signal having a frequency equal to the product of said reference frequency and said integer divider value ‘N’
- characterized in that said VCO includes a control circuit for automatically adjusting its initial free-running frequency in response to changes in said integer divider value such that the frequency difference between initial free-running VCO frequency divided by said integer divider value and said reference-frequency, is maintained at an approximately constant defined value, resulting in a controllable lock time that is independent of said integer divider value.
A method for improving a phase locked loop (PLL) by automatically adjusting the initial free-running frequency of its voltage controlled oscillator (VCO) in response to changes in the value of the integer frequency divider in the loop such that the initial free-running frequency divided by the integer divider value is maintained at an approximately constant controllable difference relative to the reference frequency, so as to provide a controllable lock time that is independent of said integer divider value.
Dependencies are inferred from the claim text.