Gain block with stable internal bias from low-voltage power supply

A method of biasing a first transistor having a control terminal, a current-sink terminal, and a current-source terminal and capable of operating from a power supply having positive and ground terminals via a bias circuit including a second transistor connected in a current-mirror configuration with the first transistor, the method comprising the steps of:

• a. monitoring an electrical characteristic at the current-sink terminal of the second transistor;
• b. amplifying the monitored characteristic;
• and
• c. feeding back the amplified characteristic to control the second transistor.

A circuit for biasing one or more transistors, the circuit comprising:

• a regulated low voltage supply terminal providing a reference current to a first transistor in a current mirror configuration;
• an amplifier providing feedback to counteract variations;
• a Darlington arrangement comprising a second transistor concurrently in the current mirror configuration;
• an input coupled to at least one transistor in the Darlington arrangement;
• an output terminal;
• and
• a power supply connected to the second transistor and providing a biasing current to the Darlington arrangement in accordance with a mirror current to the second transistor in the current mirror configuration.

A method for designing a circuit for biasing a Darlington arrangement, the method comprising:

• providing a reference current through a master transistor;
• providing a mirror current substantially related to the reference current by a scaling factor through a first transistor in the Darlington arrangement;
• and
• providing a biasing current through a second transistor coupled to the first transistor in the Darlington arrangement.

A circuit for biasing a plurality of transistors, the circuit comprising:

• a regulated low voltage supply terminal providing a reference current to a first transistor in a current mirror configuration;
• an amplifier providing feedback to counteract variations;
• a cascade arrangement of transistors comprising a second transistor concurrently in the current mirror configuration;
• an input coupled to at least one transistor in the cascade arrangement of transistors;
• and
• an output terminal connected to a power supply providing a biasing current to the cascade arrangement of transistors in accordance with a mirror current to the second transistor in the current mirror configuration.