Voltage controlled oscillator programmable delay cells

A programmable delay cell comprising:

• a plurality of load resistance transistors connected in parallel with one another;
• a plurality of bias current transistors connected in parallel with one another;
• a switching transistor connected in series between the plurality of load resistance transistors and the plurality of bias current transistors;
• and
• switching circuitry configured to selectively apply either a substantially fixed deactivating control signal or a variable activating control signal to at least one of the load resistance transistors.

A programmable differential delay cell comprising:

• a plurality of first load resistance transistors connected in parallel with one another;
• a plurality of second load resistance transistors connected in parallel with one another;
• a plurality of bias current transistors connected in parallel with one another;
• a first switching transistor connected in series between the plurality of first load resistance transistors and the plurality of bias current transistors;
• a second switching transistor connected in series between the plurality of second load resistance transistors and the plurality of bias current transistors;
• input circuitry configured to respectively apply first and second differential input signals as control signals to the first and second switching transistors;
• first switching circuitry configured to selectively activate at least one of each of the first and second load resistance transistors for operation in parallel with at least one other of the first and second load resistance transistors, respectively;
• and
• second switching circuitry configured to selectively activate at least one of the bias current transistors for operation in parallel with at least one other of the bias current transistors.