Multi-phase clock transmission circuit and method

A multi-phase clock transmission circuit comprising:

• a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to a phase difference between the reference clock and the clock and outputting the clock and the control signal;
• and
• a delay circuit for generating a multi-phase clock based on the clock and the control signal and outputting the multi-phase clock,
• wherein the clock generator comprises a clock generation circuit including a delay element for giving a delay according to the control signal to an input signal and outputting the resultant signal, the clock generation circuit generating a signal having a frequency equal to an integral multiple of a frequency of the reference clock and outputting the signal as the clock, and
• the delay circuit comprises a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal and outputting the resultant signal, signals output from the plurality of delay elements being used as signals constituting the multi-phase clock.