Direction sensitive and phase-inversion free phase detectors

Abstract

The invention relates to a new phase detector state machine having a reset state that is released only when both phase detector input signals (R, V) have a common predetermined signal state. In this way, phase inversion is effectively prevented. The complementary phase erros is properly masked and the phase detector range is reduced to the interval −180°<θe<180°, while still maintaining the direction sensitivity. Phase errors θe larger than half a period are automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector will be shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.

Dependencies are inferred from the claim text.