Method and apparatus for debugging a chip

An apparatus adapted to multiplex debug signals of an integrated circuit, the apparatus comprising:

• at least a first multiplexing circuit and a second multiplexing circuit, wherein:
• the first multiplexing circuit is adapted to receive first debug signals from an integrated circuit and to selectively multiplex at least a first portion of the first debug signals onto a first bus;
• and
• the second multiplexing circuit is adapted to receive second debug signals from the integrated circuit and to selectively multiplex at least a first portion of the second debug signals onto a second bus;
• a logic circuit adapted to combine any debug signals of the first bus and any debug signals of the second bus onto a third bus;
• and
• a third multiplexing circuit adapted to receive debug signals of the third bus and to selectively multiplex the debug signals onto a fourth bus.

A method of multiplexing debug signals of an integrated circuit, the method comprising:

• receiving first debug signals from an integrated circuit;
• selectively multiplexing at least a first portion of the first debug signals onto a first bus;
• receiving second debug signals from the integrated circuit;
• selectively multiplexing at least a first portion of the second debug signals onto a second bus;
• combining any debug signals of the first and second buses onto a third bus;
• and
• selectively outputting debug signals of the third bus.

A method of multiplexing debug signals of an integrated circuit, the method comprising:

• receiving first debug signals from an integrated circuit;
• selectively multiplexing at least a first portion of the first debug signals onto a first bus;
• receiving second debug signals from the integrated circuit;
• selectively multiplexing at least a first portion of the second debug signals onto a second bus;
• combining any debug signals of the first and second buses onto a third bus;
• and
• selectively multiplexing the debug signals onto a fourth bus.