Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device, comprising the steps of:

• forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed;
• forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a first resist pattern formed on said second interlayer insulation film;
• removing said first resist pattern and then. forming a trench pattern through etching of said second interlayer insulation film using a second resist pattern formed on said second interlayer insulation film;
• depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern;
• depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern;
• and
• removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
• at least one of said first interlayer insulation film and said second interlayer insulation film is a low dielectric film having a bond of Si and a group made of organic constituents;
• and
• a plasma treatment is performed before said barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of said low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.

A manufacturing method of a semiconductor device, comprising the steps of:

• depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed;
• forming a hard mask through etching of said hard mask material using a first resist pattern formed on said hard mask material;
• forming a via hole penetrating through said first interlayer insulation film and said second-interlayer insulation film using a second resist pattern formed on said hard mask;
• removing said second resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using said hard mask;
• depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern;
• and
• depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern;
• and
• removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
• at least one of said first interlayer insulation film, said second interlayer insulation film, and said hard mask is a low dielectric film having a bond of Si and a group made of organic constituents;
• and
• a plasma treatment is performed before said barrier metal is deposited, using one of a gas. capable of replacing at least part of the group made of organic constituents on an exposed surface of said low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.