Enhanced chip scale package for wire bond dies

A chip scale package assembly comprising:

• an integrated circuit die having bond wires for electrically interconnecting with said die;
• a carrier for electrically interconnecting said die with a primary circuit board, said carrier comprising:
• a substrate comprising top and bottom sides, said top side comprising a die mounting area to receive said die;
• wire bond fingers on said top side of said substrate to receive said bond wires from said die;
• signal pads on said bottom side of said substrate electrically coupled to said wire bond fingers;
• a first ground plane generally covering said top side of said substrate but leaving exposed said wire bond fingers;
• a second ground plane generally covering a central area of said bottom side of said substrate, said signal pads generally arrayed about said second ground plane;
• ground pads on said bottom side of said substrate, said ground pads positioned within and electrically coupled to said second ground plane;
• and
• thermal vias positioned within said die mounting area thermally and electrically coupling said first and second ground planes.

A chip scale package carrier for electrically and thermally coupling an integrated circuit die having bond wire signal connections and at least one ground connection to a primary circuit board, said carrier comprising:

• a mounting area on a top side of said carrier to receive the die;
• a plurality of wire bond fingers on said top side of said carrier to receive bond wires interconnecting the signal connections on the die with respective ones of said plurality of wire bond fingers;
• a plurality of signal pads on a bottom side of said carrier, respective ones of said plurality of said signal pads electrically coupled to respective ones of said wire bond fingers;
• a first ground plane generally covering said top side of said carrier, said first ground plane leaving said wire bond fingers exposed for interconnection with the bond wires;
• a second ground plane covering a central area of said bottom side of said carrier, said signal pads on said bottom side generally arrayed around said second ground plane;
• a plurality of thermal vias positioned within said mounting area and extending through said carrier to electrically and thermally couple said first and second ground planes;
• and
• a plurality of ground pads on said bottom side of said carrier, said plurality of ground pads positioned within an area defined by said second ground plane and electrically coupled to said second ground plane.

A carrier for interconnecting an integrated circuit die with a circuit board, comprising:

• a) a substrate having a top surface;
• b) a plurality of signal points disposed on the top surface of the substrate for interfacing with the integrated circuit die;
• c) the plurality of signal points being disposed in groups with each group of signal points being spaced from an adjacent group;
• and
• d) a ground plane disposed generally around each of the groups of signal points and extending over a substantial area of the top surface of the substrate, the ground plane operative to ground the integrated circuit die.