Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, comprising:

• forming an element isolation region in the process of manufacturing a MOS transistor using an SOI substrate;
• forming a well only in a body region below a gate electrode of the MOS transistor which is to be formed later in a semiconductor thin film;
• forming a gate insulating film on the semiconductor thin film;
• doping the semiconductor thin film with an impurity to control the threshold voltage;
• depositing polycrystalline silicon on the semiconductor thin film;
• doping a region of the polycrystalline silicon film that is to form an NMOS transistor with an n type impurity;
• doping a region of the polycrystalline silicon film that is to form a PMOS transistor with a p type impurity;
• forming a high melting point metal silicide film on the polycrystalline silicon film;
• patterning the polycrystalline silicon film and the high melting point metal silicide film to form the gate electrode with a laminate structure;
• lightly doping regions of the polycrystalline silicon film that are to serve as a source and drain of the NMOS transistor with an n type impurity to form first conductivity type low concentration impurity diffusion layers, the first conductivity type being the n type;
• lightly doping regions of the polycrystalline silicon film that are to serve as a source and drain of the PMOS transistor with a p type impurity to form second conductivity type low concentration impurity diffusion layers, the second conductivity type being the p type;
• forming an insulating film by deposition on the SOI substrate;
• etching the insulating film by anisotropic dry etching to form a side spacer on a side wall of the gate electrode that is a laminate of the polycrystalline silicon film and the high melting point metal silicide film;
• heavily doping the regions to serve as the source and drain of the NMOS transistor with an n type impurity to form first conductivity type high concentration impurity diffusion layers, the first conductivity type being the n type;
• and
• heavily doping the regions to serve as the source and drain of the PMOS transistor with a p type impurity to form second conductivity type high concentration impurity diffusion layers, the second conductivity type being the p type.

A method of manufacturing a semiconductor device, comprising:

• forming an element isolation region in the process of manufacturing a MOS transistor using an SOI substrate;
• forming a well only in a body region below a gate electrode of the MOS transistor which is to be formed later in a semiconductor thin film;
• forming a gate insulating film on the semiconductor thin film;
• doping the semiconductor thin film with an impurity to control the threshold voltage;
• depositing polycrystalline silicon on the semiconductor thin film and patterning the obtained polycrystalline silicon film to form the gate electrode;
• selectively and lightly doping regions of the polycrystalline silicon film that are to serve as a source and drain of an NMOS transistor, or the drain region alone, with an n type impurity to form a first conductivity type low concentration impurity diffusion layer(s), the first conductivity type being the n type;
• selectively and lightly doping regions of the polycrystalline silicon film that are to serve as a source and drain of a PMOS transistor, or the drain region alone, with a p type impurity to form a second conductivity type low concentration impurity diffusion layer(s), the second conductivity type being the p type;
• selectively and heavily doping regions of the NMOS transistor where the source and the drain do not overlap the gate electrode flatly, or regions of the NMOS transistor where the source side overlaps the gate electrode flatly but not the drain side, with an n type impurity to form first conductivity type high concentration impurity diffusion layers, the first conductivity type being the n type;
• and
• selectively and heavily doping regions of the PMOS transistor where the source and the drain do not overlap the gate electrode flatly, or regions of the PMOS transistor where the source side overlaps the gate electrode flatly but not the drain side, with a p type impurity to form second conductivity type high concentration impurity diffusion layers, the second conductivity type being the p type.

A method of manufacturing a semiconductor device, comprising:

• forming an element isolation region in the process of manufacturing a MOS transistor using an SOI substrate;
• forming a well only in a body region below a gate electrode of the MOS transistor which is to be formed later in a semiconductor thin film;
• forming a gate insulating film on the semiconductor thin film;
• doping the semiconductor thin film with an impurity to control the threshold voltage;
• depositing polycrystalline silicon on the semiconductor thin film;
• doping a region of the polycrystalline silicon film that is to form an NMOS transistor with an n type impurity;
• doping a region of the polycrystalline silicon film that is to form a PMOS transistor with a p type impurity;
• forming a high melting point metal silicide film on the polycrystalline silicon film;
• patterning the polycrystalline silicon film and the high melting point metal silicide film to form the gate electrode with a laminate structure;
• selectively and lightly doping regions of the polycrystalline silicon film that are to serve as a source and drain of an NMOS transistor, or the drain region alone, with an n type impurity to form a first conductivity type low concentration impurity diffusion layer(s), the first conductivity type being the n type;
• selectively and lightly doping regions of the polycrystalline silicon film that are to serve as a source and drain of a PMOS transistor, or the drain region alone, with a p type impurity to form a second conductivity type low concentration impurity diffusion layer(s), the second conductivity type being the p type;
• selectively and heavily doping regions of the NMOS transistor where the source and the drain do not overlap the gate electrode flatly, or regions of the NMOS transistor where the source side overlaps the gate electrode flatly but not the drain side, with an n type impurity to form first conductivity type high concentration impurity diffusion layers, the first conductivity type being the n type;
• and
• selectively and heavily doping regions of the PMOS transistor where the source and the drain do not overlap the gate electrode flatly, or regions of the PMOS transistor where the source side overlaps the gate electrode flatly but not the drain side, with a p type impurity to form second conductivity type high concentration impurity diffusion layers, the second conductivity type being the p type.