Self-aligned punch through stop for 6F2 rotated hybrid dram cell

A method of forming a memory cell array comprising the steps of:

• forming double-gated vertical MOSFETs in a plurality of deep trenches that are present in a Si-containing substrate, wherein said double-gated vertical MOSFETs include at least two gates on opposing sidewalls, exposed gate conductors and a buried-strap region;
• forming wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductors;
• forming bitlines on said Si-containing substrate that are orthogonal to said wordlines;
• etching isolation trench regions into portions of said Si-containing substrate that are adjacent to rows of deep trenches using said wordlines and bitlines as etch masks, said isolation trench regions having a depth that is deeper than abutting bitline diffusion regions;
• and
• forming punch through stop regions into said etched isolation trench regions using said bitlines and wordlines as implant masks, said punch through stop regions are capable of isolating adjacent buried straps from each other and are centrally located about the deep trenches in areas adjacent to said gates, wherein neighboring punch through stop regions in the wordline direction overlap each other under the bitlines.