Semiconductor display device and manufacturing method method thereof

A semiconductor device comprising a plurality of n-channel thin film transistors formed on a transparent insulating substrate, each of the n-channel thin film transistors comprising:

• a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode,
• wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located on the first layer gate electrode and the first layer gate electrode is formed to have a loneer size in a channel direction than the second layer gate electrode,
• wherein a first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the gate electrode,
• wherein a second impurity region and a third impurity region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer corresponding to the outside of the gate electrode, and
• wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the third impurity region.

A method of manufacturing a semiconductor device comprising:

• laminating a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film over a transparent insulating substrate in order from a side near the transparent insulating substrate;
• forming a resist pattern for gate electrode formation over the substrate with the laminated structure;
• performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode;
• ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode;
• performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode;
• performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignment;
• ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode;
• removing the negative resist pattern;
• and
• ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode.

A method of manufacturing a semiconductor device comprising:

• forming a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film on a transparent insulating substrate in order from a side near the transparent insulating substrate;
• forming a resist pattern for gate electrode formation on the substrate with a resultant structure;
• performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode;
• ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode;
• performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode;
• ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode;
• performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignmnent;
• and
• ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode.

A method of manufacturing a semiconductor device comprising:

• forming a semiconductor layer over a substrate;
• forming a gate insulating film on the semiconductor layer;
• forming a gate electrode on the gate insulating film, the gate electrode comprising a first conductive layer and a second conductive layer formed on the first conductive layer;
• forming a negative resist over the substrate;
• performing rear surface exposure using the gate electrode as a mask to form a negative resist pattern in a self alignment;
• introducing an impurity into first impurity regions in the semiconductor using the second conductive layer and the negative resist pattern as masks;
• removing the negative resist pattern;
• and
• introducing the impurity into the first impurity regions and second impurity regions in the semiconductor layer using the second conductive layer as a mask.

A method of manufacturing a semiconductor device comprising:

• forming a semiconductor layer over a substrate;
• forming a gate insulating film on the semiconductor layer;
• forming a gate electrode on the gate insulating film, the gate electrode comprising a first conductive layer and a second conductive layer formed on the first conductive layer;
• introducing an impurity into the first impurity regions and second impurity regions in the semiconductor layer using the second conductive layer as a mask;
• forming a negative resist over the substrate;
• performing rear surface exposure using the gate electrode as a mask to form a negative resist pattern in a self alignment;
• and
• introducing the impurity into first impurity regions in the semiconductor using the second conductive layer and the negative resist pattern as masks.