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US 2003/0155589 A1Published application
Silver-selenide/chalcogenide glass stack for resistance variable memory
AssigneeMicron Technology, Inc.
InventorsKristy A. Campbell, John T. Moore
Life of this patent
Estimating the term…
Abstract
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100−x composition.
Claims142
A resistance variable memory element comprising:
- at least one metal containing layer, at least one chalcogenide glass layer, at least one other glass layer, said metal containing layer being provided between said at least one chalcogenide glass layer and said at least one other glass layer.
A resistance variable memory element comprising:
- a body, said body comprising a first glass layer in contact with at least one silver-chalcogenide layer, said silver-chalcogenide layer being in contact with a second glass layer, wherein at least one of said first and second glass layers is a formed of a chalcogenide glass material;
- and
- a first electrode and a second electrode in respective contact with said first and second glass layers.
A memory element comprising:
- a first electrode;
- a first glass layer comprising GexSe100−x, wherein x=20 to 43 said first glass layer being in contact with said first electrode;
- a first metal containing layer in contact with said first glass layer;
- a second glass layer in contact with said first metal containing layer;
- and
- a second electrode in contact with said second glass layer.
3 more elements
A chalcogenide glass stack comprising:
- a chalcogenide glass layer;
- at least one metal containing layer in contact with said chalcogenide glass layer;
- and
- a diffusion control layer in contact with said metal containing layer for controlling diffusion of elements into said chalcogenide glass layer.
1 more element
A memory element comprising:
- a first electrode;
- at least one first chalcogenide glass layer in contact with said first electrode;
- at least one first metal containing layer in contact with said at least one first chalcogenide glass layer;
- at least one second chalcogenide glass layer in contact with said at least one first metal containing layer;
- at least one second metal containing layer in contact with said at least one second chalcogenide glass layer;
- at least one third chalcogenide glass layer in contact with said at least one second metal containing layer;
- and
- a second electrode in contact with said at least one third chalcogenide glass layer.
5 more elements
A method of forming a resistance variable memory element comprising the steps of:
- forming a first electrode;
- forming a first chalcogenide glass layer in contact with said first electrode;
- forming a first metal containing layer in contact with said first chalcogenide glass layer;
- and
- forming a second chalcogenide glass layer in contact with said first metal containing layer;
- forming a second metal containing layer in contact with said first chalcogenide glass layer;
- forming a third chalcogenide glass layer in contact with said second metal containing layer;
- and
- forming a second electrode in contact with said third chalcogenide glass layer.
6 more elements
A method of forming a resistance variable memory element comprising:
- forming a first glass layer;
- forming a silver-selenide layer in contact with said first glass layer;
- and
- forming a second glass layer in contact with said silver-selenide layer, whereby one of said first and second glass layers is a formed of a chalcogenide glass material.
1 more element
A processor-based system, comprising:
- a processor;
- and
- a memory circuit connected to said processor, said memory circuit including a resistance variable memory element comprising at least one metal containing layer, at least one chalcogenide glass layer, at least one other glass layer, said metal containing layer being provided between said at least one chalcogenide glass layer and said at least one other glass layer.
A processor-based system, comprising:
- a processor;
- a memory circuit connected to said processor, said memory circuit including a first electrode;
- at least one first chalcogenide glass layer in contact with said first electrode;
- at least one first metal containing layer in contact with said at least one first chalcogenide glass layer;
- at least one second chalcogenide glass layer in contact with said at least one first metal containing layer;
- at least one second metal containing layer in contact with said at least one second chalcogenide glass layer;
- at least one third chalcogenide glass layer in contact with said at least one second metal containing layer;
- and
- a second electrode in contact with said at least one third chalcogenide glass layer.
6 more elements
A memory element comprising:
- a first electrode;
- a second electrode;
- and
- a plurality of chalcogenide glass layers and a plurality of metal containing layers between said first and second electrodes, whereby said plurality of chalcogenide glass layers alternate with said metal containing layers, with one of said chalcogenide glass layers in contact with said first electrode and another of said chalcogenide glass layers in contact with said second electrode.
1 more element
A method of forming a resistance variable memory element comprising:
- forming a first electrode;
- forming a second electrode;
- and
- forming a plurality of chalcogenide glass layers and a plurality of metal containing layers between said first and second electrodes, whereby said plurality of chalcogenide glass layers alternate with said metal containing layers, with one of said chalcogenide glass layers in contact with said first electrode and another of said chalcogenide glass layers in contact with said second electrode.
1 more element
Dependencies are inferred from the claim text.