Apparatus and method for improved execution of a software pipeline loop procedure in a digital signal processor

The processor as recited in claim 4 further comprising an second instruction, the second instruction indicating when the transition from the first to the second state is to occur, the second instruction further delaying the program counter a predetermined number of clock cycles following the end of the second state.

An instruction for inclusion in a software pipeline loop program, the instruction initiating a first prolog state of the processor implementing the software pipeline procedure, the initiating the first state including storing of a termination condition value in a termination condition register, the instruction disabling a test of a value stored in the termination condition register.

An instruction for inclusion in a software pipeline loop program, the instruction resulting in a transition from a SP_PROLOG state to an SP_KERNAL state, the instruction including a parameter delaying the initiation of the program counter for a predetermined number of clock cycles after identification of the termination condition.

A method of reducing the number of NOP instructions associated with software pipelined loop program, the method comprising at least one procedure selected from the list of procedure consisting of:

• initiating the software loop program with a first instruction disabling from testing a value in a termination condition register, the value in the termination condition register identifying the number of times that each instruction stage is to be performed;
• and
• transitioning from the SP_PROLOG state to the SP_KERNAL state using a second instruction, the second instruction including a parameter delaying the initiation of the fetching of instructions by a program following the software pipeline procedure by a preselected number of clock cycles following the end of the SP_KERNAL state.

The method for delaying the fetching of instruction packets of a following program following a software pipeline loop program, the method comprising:

• inserting kernel instruction in the last execution packet of the last instruction stage, the kernel instruction identifying the delay parameter;
• and
• when the delay parameter is present, fetching instruction packets for the following program.

The method compensating for hardware pipeline delays in executing a software pipeline loop procedure, the method comprising:

• inserting a SPLOOPD instruction to initiate a prolog procedure, the SPLOOP instruction including a delay parameter, the SPLOOPD instruction including a test for portion for testing a condition;
• and
• delaying execution of the test portion by the delay parameter.