Method and system for verifying modules destined for generating circuits

Method in accordance with any of the preceding claims, characterised in that it also includes the following steps:

• selecting, a description in VHDL (200) as said synthesizable description.
• providing(100) a set of classes, each of which is capable of representing an instruction or a construct of the VHDL description of the modules to be verified, each class containing an internal parsing function, and at least one SystemC conversion function,
• applying the parsing function to the VHDL code for each of said classes, so as to recognise corresponding instructions or constructs,
• once an instruction or a construct is recognised, to memorise the relevant information thus obtained according to the hierarchical structure of the VHDL, and
• applying the conversion function to SystemC to said information while keeping said hierarchical structure, so as to generate, by the effect of the conversion to SystemC, said C++ model that keeps the VHDL hierarchical structure.