Multiprocessor system with cache-based software breakpoints

A multiprocessor system comprising:

• a main memory;
• and
• a plurality of processors each coupled to the main memory, each of the processors having an instruction cache associated therewith;
• wherein an instruction, for which the breakpoint is to be inserted, is retrievable from a corresponding instruction address in the main memory;
• wherein a breakpoint code is insertable at the instruction address in main memory;
• and
• wherein subsequent to execution of the breakpoint code by the given processor, the retrieved instruction is stored in the corresponding instruction cache for that processor, and a use-once indicator associated with the instruction as stored in the corresponding instruction cache for that processor is set, wherein the use-once indicator, when set for the instruction as stored in the instruction cache, is operative via cache control logic to clear a validity indicator associated with the instruction after a single fetch of the instruction from the instruction cache, such that subsequent attempts by the given processor to access the instruction as stored in the instruction cache will cause the processor to retrieve the breakpoint code at the instruction address in main memory.

An article of manufacture comprising a machine-readable storage medium for storing one or more software programs for implementing a software breakpoint in a multiprocessor system having a plurality of processors each coupled to a main memory, each of the processors having an instruction cache associated therewith, wherein the one or more software programs when executed implement the steps of:

• retrieving an instruction, for which the breakpoint is to be inserted, from a corresponding instruction address in the main memory;
• inserting a breakpoint code at the instruction address in main memory;
• and
• after the breakpoint code is executed by a given one of the processors, storing the retrieved instruction in the corresponding instruction cache for that processor and setting a use-once indicator associated with the instruction as stored in the corresponding instruction cache for that processor, wherein the use-once indicator, when set for the instruction as stored in the instruction cache, is operative via cache control logic to clear a validity indicator associated with the instruction after a single fetch of the instruction from the instruction cache, such that subsequent attempts by the given processor to access the instruction as stored in the instruction cache will cause the processor to retrieve the breakpoint code at the instruction address in main memory.