Method for designing semiconductor integrated circuit and method for testing the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorTakaki Yoshida
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Abstract
A method is provided for designing a semiconductor integrated circuit including a plurality of clock groups which are designed to be supplied with their respective clock signals. The method is improved by supplying plural kinds of clock signals for performing a scan testing respectively to the clock groups, the respective clock signals having different duty factors in at least a part of the clock groups. This prevents circuits on the plurality of scan lines from operating simultaneously, thus suppressing power consumption during a clock operation, allowing highly accurate testing.
Claims11
In a method for designing a semiconductor integrated circuit including a plurality of clock groups which are designed to be supplied with their respective clock signals;
- the improvement comprising:
- supplying plural kinds of clock signals for performing a scan testing respectively to the clock groups, the respective clock signals having different duty factors at least in a part of the clock groups.
In a method for testing a semiconductor integrated circuit by inputting clock signals for performing a scan testing respectively to a plurality of scan lines included in the semiconductor integrated circuit, the improvement comprising:
- supplying plural kinds of clock signals for performing the scan testing respectively to the scan lines, the respective clock signals having different duty factors at least in a part of the scan lines.
Dependencies are inferred from the claim text.